APPARATUS FOR TESTING MODULATOR DEMODULATOR UNITS FOR TRANSMISSION ERRORS AND INDICATING THE ERRORS PER POWER OF 10

• US 3,622,877 A
• Filed: 11/07/1969
• Issued: 11/23/1971
• Est. Priority Date: 11/07/1969
• Status: Expired due to Term

• Current Assignee: Donald G. Shuda, John F. Leaver Jr, Kenneth R. Macdavid
• Original Assignee: Donald G. Shuda, John F. Leaver Jr, Kenneth R. Macdavid
• Inventors: MacDavid, Kenneth R., Shuda, Donald G., Leaver, John F. Jr.
• Primary Examiner(s): Lynch, Michael J.
• Assistant Examiner(s): Corcoran, R. J.
• Application Number:
  US04/874,839
• Time in Patent Office: 746 Days
• Field of Search: 340/146.1 325/41,67 178/23.1 324/73R
• US Class Current: 375/222
• CPC Class Codes: H04L 1/241 using pseudo-errors
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica

Abstract

Test apparatus for testing and recording either accumulated errors or the probability of error for either synchronous or asynchronous digital data modulator/demodulator units (modems). The modem tester includes a test generator which under the control of a bit rate selector and a sequence mode selector generates a bit test sequence. The bit test sequence is modulated by the modulator portion of a modem under test and is then applied to the demodulator portion of either the same or a different modem under test. The modem tester further includes a reference bit sequence generator and a data synchronization network responsive to the bit test sequence after demodulation for synchronizing the reference bit sequence generator with the test sequence received from the demodulator under test. The received test sequence and the referenced sequence are compared with disagreements of the comparison being accumulated in an error counter. For testing asynchronous modems, a bit synchronization network is provided to maintain the sampling window of the comparator at substantially the middle of a bit period. In order to display probability of error, the mode sequence selector is settable to any one of plural total bits indicia expressed as powers of 10 on the display panel. A total bit counter responds to such settings to inhibit further operation of the error counter after a number of bit periods equal to the setting of the selector such that the total errors per power of 10 bits is displayed directly on the display panel.

Claims

1. A tester for testing a transmission path including a modulator unit and a demodulator unit by applying a bit test sequence to the path and receiving therefrom said test sequence after modulation and demodulation by said unitS, comprising;

a source of clock signals, first means responsive to said clock signals for generating said bit test sequence for application to said transmission path under test;

second means responsive to said clock signals for generating a reference bit sequence identical to said test bit sequence;

comparator means enabled during each bit period by a sampling pulse to compare a sample of said reference sequence and of said received sequence, synchronization means including 1. means for synchronizing said reference sequence generating means with said received bit sequence; and

2. means responsive to said received bit sequence and to said clock signals for producing said sampling pulse substantially in the middle of a bit period;

means responsive to said comparator means for accumulating errors of disagreement between the samples of the reference and received bit sequences; and

a display panel including means responsive to said error accumulating means for displaying accumulated errors.

2. The invention according to claim 1 wherein a selector mounted on said display panel is settable to any one of a plurality of bit sequences according to indicia adjacent thereto on said display panel;

and wherein each of said first and second means includes programmable means responsive to said selector for generating a selected one of said plurality of bit sequences.

3. The invention according to claim 2 wherein said selector is further settable to any one of plural total bits indicia expressed as powers of 10 on said panel;

and wherein means responsive to said selector being placed in a total bits setting inhibits further operation of said error accumulator after a number of bit periods equal to the setting of said selector whereby the total errors per power of 10 bits is displayed directly on said panel.

4. Test apparatus for testing a transmission path including a modulator unit and a demodulator unit by applying a test bit sequence to the path and receiving therefrom said test sequence after modulation and demodulation by said units, comprising first means for generating said test bit sequence for application to said transmission path under test;

second means for generating a reference bit sequence identical to said test bit sequence;

comparator means for comparing samples of said reference sequence and of said received sequence during each bit period;

synchronization means for synchronizing said reference sequence generating means with said received bit sequence;

means responsive to said comparator means for accumulating errors of disagreement between the reference and received bit sequences;

a display panel having first means mounted thereon responsive to said error accumulating means for displaying accumulated errors and having further mounted thereon a selector which is settable to any one of a plurality of total bits indicia expressed as powers of 10 on said panel; and

means responsive to said selector being placed in total bits setting for inhibiting further operation of said error accumulator after a number of bit periods equal to the setting of said selector whereby the total errors per power of 10 bits is displayed directly on said panel.