FAIL-SAFE VEHICLE BRAKE ASSURING

• US 3,626,177 A
• Filed: 05/22/1970
• Issued: 12/07/1971
• Est. Priority Date: 05/22/1970
• Status: Expired due to Term

• Current Assignee: Union Switch & Signal, Inc. (Hitachi, Ltd.)
• Original Assignee: Raymond C. Franke
• Inventors: Franke, Raymond C.
• Primary Examiner(s): La Point, Arthur L.
• Assistant Examiner(s): Libman, George H.
• Application Number:
  US05/039,790
• Time in Patent Office: 564 Days
• Field of Search: 303/20 246/182B,182C
• US Class Current: 246/1.00R
• CPC Class Codes: B60T 13/665 the systems being specially adapted for transferring two or more command signals, e.g. railway systems B60T13/662 takes precedence
• CPC Class Codes: B60T 17/20 Safety devices operable by passengers other than the driver , e.g. for railway vehicles

Abstract

This invention relates to a fail-safe vehicle brake assuring circuit for assuring that a vehicle is decelerating at a sufficient rate to a predetermined speed along a predetermined path. The circuit comprises a speed measuring device coupled to the vehicle and electrically coupled to a redundant channel deceleration detection network, which is, in turn coupled to an interlocking circuit having an output. The interlocking circuit also receives a vehicle overspeed signal input and a zero velocity input signal. The absence of an output signal on the output of the interlocking circuit is indicative of insufficient vehicle deceleration or of any speed condition coupled with a component failure in the brake assuring circuit.

Claims

1. A fail-safe vehicle brake assuring circuit for assuring that a vehicle is decelerating at a sufficient rate to a predetermined speed along a predetermined path said circuit comprising:

a. speed measuring means coupled to said vehicle and having an output signal the frequency of which is proportional to vehicle speed, b. redundant channel deceleration detection means having at least a first and a second detection channel each receiving said output signal from said axle generator means, said first and said second detection channels having respective outputs, said outputs of said first and said second detection channels each having a first and a second state, said second state appearing only when the rate of change of said frequency of said axle generator output signal with respect to time is greater than a predetermined value, c. interlocking means coupled to said redundant channel deceleration detection means via said first and said second detection channel outputs, said interlocking means receiving an overspeed signal from said vehicle whenever said vehicle is traveling at a speed greater than a preselected authorized speed, and a zero velocity signal from said vehicle whenever said vehicle is traveling at less than a very low predetermined speed, said interlocking means producing an output only when the states on each of said first and said second deceleration detection channel outputs are in agreement, said interlocking means producing no output whenever the state of said first deceleration detection channel output and the state of said second deceleration detection channel output are in disagreement for longer than a preselected time period, or whenever said first and said second deceleration detection channel outputs are in said first state while said interlocking means receives said overspeed signal for longer than said preselected time period, or whenever said first and said second deceleration detection channel outputs are in said second state while said interlocking means receives said zero velocity signal for longer than said preselected time period, or whenever any speed condition concurs with a component failure in said brake assuring circuit.

2. The fail-safe brake assuring circuit of claim 1 wherein first and second detection channels of said redundant channel deceleration detection means include respectively, a. first and second digital-to-analog conversion means electrically coupled to said speed measuring means to receive said output signal the frequency of which is proportional to vehicle speed, each of said first and second conversion means having an output, said conversion means converting said output signal to analog signals indicative of vehicle speed and appearing on said outputs of said first and second digital-to-analog conversion means, b. first and second derivative taking means each having an output respectively receiving said first and second digital-to-analog conversion means outputs and differentiating said digital-to-analog conversion means outputs with respect to time to provide signals indicative of vehicle deceleration appearing on said outputs of said first and second derivaTive taking means, c. first and second level detecting means each having an output respectively receiving said first and second derivative taking means outputs, said first and second level detecting means each preset at the same preselected threshold value to provide signals on said outputs of said first and second level detecting means whenever the magnitude of said signals on said first and second derivative taking means outputs exceed said preselected threshold value, d. first and second interlocking circuit control means controllingly coupled to said interlocking means respectively having first and second states and respectively electrically coupled to said outputs of said first and second level detecting means, said first and second interlocking circuit control means being in said first state whenever said outputs of said first and second level detector means have signals appearing thereon, said first and second interlocking circuit control means being in said second state whenever said outputs of said first and second level detector means have no signals appearing thereon.

3. The fail-safe brake assuring circuit of claim 1 wherein said interlocking means includes timing control means to assure the absence of an output from said interlocking means at the end of said preselected time period whenever the state of said first deceleration detection channel output and the state of said second deceleration detection channel output are in disagreement for longer than said preselected time period, or whenever said first and said second deceleration detection channel outputs are in said first state while said interlocking means receives said overspeed signal for longer than said preselected time period, or whenever said first and said second deceleration detection channel outputs are in said second state while said interlocking means receives said zero velocity signal for longer than said preselected time period, or whenever any speed condition concurs with a component failure in said brake assuring circuit.

4. The fail-safe brake assuring circuit of claim 1 wherein said speed measuring means comprises a driving link rotatably coupled to an axle of said vehicle and providing an input indicative of vehicle velocity to a mechanical to electrical converting circuit having an electrical output indicative of vehicle speed.

5. The fail-safe brake assuring circuit of claim 1 wherein said first and second interlocking circuit control means are electromagnetic devices.

6. The fail-safe brake assuring circuit of claim 5 wherein said first and second interlocking control means are relays.

7. The fail-safe brake assuring circuit of claim 3 wherein said timing control means comprises a timing control electromagnetic device and a resistor-capacitor series circuit electrically coupled to said timing control electromagnetic device.

8. The fail-safe brake assuring circuit of claim 7 wherein said timing control electromagnetic device is a relay.

9. The fail-safe brake assuring circuit of claim 1 wherein a proper braking indication circuit is electrically coupled to said output of said interlocking means to provide an indication of proper vehicle braking operation.