MULTIPLE IMAGE REGISTRATION SYSTEM

• US 3,627,918 A
• Filed: 10/30/1969
• Issued: 12/14/1971
• Est. Priority Date: 10/30/1969
• Status: Expired due to Term

• Current Assignee: Donald Clark Redpath
• Original Assignee: Donald Clark Redpath
• Inventors: Redpath, Donald Clark
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Orsino, Jr., Joseph A.
• Application Number:
  US04/872,621
• Time in Patent Office: 775 Days
• Field of Search: 356/2,167,203,206 250/22SP 178/6.5,6.8 235/181
• US Class Current: 348/47
• CPC Class Codes: G01C 11/00 Photogrammetry or videogrammetry, e.g. stereogrammetry; Photographic surveying

Abstract

An image registration system in which scanning patterns directed through a pair of images are used in a conventional manner to generate video signals that are in turn correlated and analyzed producing error signals. The error signals are then differentially modulated with reference signals producing modulated and complementary modulated error signals of opposite polarity. Selective combination of the reference and modulated error signals is accomplished with low noise and relatively simple circuitry and results in balanced pairs of deflection signals that induce equal but opposite transformations of the scanning patterns in senses tending to eliminate relative image distortion represented by the error signals.

Claims

1. An image registration system comprising scanning means for simultaneously directing first and second scanning beams over corresponding paths in a pair of images having relatively homologous detail content, signal generating means for producing first and second video signals representing image detail in the corresponding paths scanned by said scanning beams, correlation means adapted to correlate said first and second video signals and to produce a raw error signal indicative of composite misregistration between the image detail in the corresponding paths, waveform generator means for producing a reference signal, analyzer means for analyzing said raw error signal with respect to said reference signal and for producing parallax error signals representing particular types of misregistration between the image detail in the corresponding paths, modulation means adapted to differentially modulate said analyzed error signals with said reference signal producing modulated error signals of opposite polarity, and combining means connected to combine said modulated error signals with said reference signal and adapted to produce therewith deflection signals that are applied to said scanning means.

2. An image registration system according to claim 1 wherein said deflection signals comprise one deflection signal having a value proportional to the algebraic summation of said reference signal and said modulated error signals of one polarity and another deflection signal having a value proportional to the algebraic summation of said reference signal and a complementary modulated error signals of the opposite polarity.

3. An image registration system according to claim 2 wherein said scanning means comprises a first deflection control means for deflecting said first scanning beam and a second deflection control means for deflecting said second scanning beam, said one deflection signal is applied to said first deflection control means, and said another deflection signal is applied to said second deflection control means.

4. An image registration system according to claim 3 wherein said modulation means is adapted to produce amplitude modulation of said analyzed error signals.

5. An image registration system according to claim 4 wherein said modulation means produces said modulation by multiplying said analyzed error signals by said reference signal.

6. An image registration system according to claim 5 wherein said modulation means comprises a plurality of modulators each connected to receive one of said analyzed error signals.

7. An image registration system according to claim 6 wherein each of said modulators comprises a dual, matched field effect transistor having common drain electrodes connected to receive one of said analyzed error signals.

8. An image regisTration system according to claim 7 wherein each of said modulators comprise a differential amplifier connected to amplify the dual outputs of said field effect transistor.

9. An image registration system according to claim 8 wherein said reference signal is applied differentially to the gate electrodes of said dual transistors.

10. An image registration system according to claim 5 wherein said combining circuit means combines said reference signal and said modulated error signals to produce a first summation signal, inverts the polarity of said reference signal and combines the resultant complementary reference signal and said complementary modulated error signals to produce a second summation signal, combines said reference signal and said complementary modulated error signals to produce a third summation signal, combines said complementary reference signal and said modulated error signals to produce a fourth summation signal, obtains the difference between said first and second summation signals to produce said one deflection signal, and obtains the difference between said third and fourth summation signals to produce said another deflection signal.

11. An image registration system according to claim 10 wherein said modulation means comprises a plurality of modulators each connected to receive one of said analyzed error signals.

12. An image registration system according to claim 11 wherein each of said modulators comprises a dual, matched field effect transistor having common drain electrodes connected to receive one of said analyzed error signals.

13. An image registration system according to claim 12 wherein each of said modulators comprise a differential amplifier connected to amplify the dual outputs of said field effect transistor.

14. An image registration system according to claim 13 wherein said reference signal is applied differentially to the gate electrodes of said dual transistors.

15. An image registration system according to claim 6 wherein said analyzer circuit means is adapted further to produce a scanning pattern size control signal, said modulator means differentially modulates said control signal with said reference signal producing modulated reference control signals of opposite polarity that are both applied to said modulators receiving said error signals so as to produce said differential modulation thereof.

16. An image registration system according to claim 15 wherein each of said modulators comprises dual, matched field effect transistor having common drain electrodes connected to receive one of said analyzed error signals.

17. An image registration system according to claim 16 wherein each of said modulators comprise a differential amplifier connected to amplify the dual outputs of said field effect transistor.

18. An image registration system according to claim 17 wherein said reference control signals of opposite polarity are applied to the gate electrodes of said dual transistors.

19. An image registration system according to claim 1 wherein said reference signal produced by said waveform generator means comprises x and y-reference signals adapted for generating scanning patterns having scanning lines oriented in orthogonally related x and y directions.

20. An image registration system according to claim 19 wherein said analyzed error signals comprise x-error signals representing image detail misregistration in the x-direction of said scanning patterns and y-error signals representing image detail misregistration in the y-direction of said scanning patterns.

21. An image registration system according to claim 20 wherein said modulation means differentially modulates said x-error signals with said x-reference signal producing modulated x-error and complementary x-error signals of opposite polarity and differentially modulates said y-error signals with said y-reference signals producing modulated y-error and coMplementary y-error signals of opposite polarity.

22. An image registration system according to claim 21 wherein said deflection signals comprise one x-deflection signal having a value proportional to the algebraic summation of said x-reference signal and said modulated x-error signals, another x-deflection signal having a value proportional to the algebraic summation of said x-reference signal and said complementary modulated x-error signals, one y-deflection signal having a value proportional to the algebraic summation of said y-reference signal and said modulated y-error signals, and another y-deflection signal having a value proportional to the algebraic summation of said y-reference signal and said complementary modulated y-error signals.

23. An image registration system according to claim 22 wherein said scanning means comprises a first deflection control means for deflecting said first scanning beam and a second deflection control means for deflecting said second scanning beam, said one x-deflection signal and said one y-deflection signal are applied to said first deflection control means, and said another x-deflection signal and said another y-deflection signal are applied to said second deflection control means.

24. An image registration system according to claim 23 wherein said modulation means is adapted to produce amplitude modulation of said x and y-error signals.

25. An image registration system according to claim 24 wherein said modulation means produces said modulation by multiplying said x-error signals by said x-reference signal and by multiplying said y-error signals by said y-reference signal.

26. An image registration system according to claim 25 wherein said combining circuit means combines said x-reference signal and said modulated x-error signals to produce a first x-summation signal, inverts the polarity of said x-reference signal and combines the resultant complementary x-reference signal and said complementary modulated x-error signals to produce a second x-summation signal, combines said x-reference signal and said complementary modulated x-error signals to produce a third x-summation signal, combines said complementary x-reference signal and said modulated x-error signals to produce a fourth x-summation signal, obtains the difference between said first and second x-summation signals to produce said one x-deflection signal, and obtains the difference between said third and fourth x-summation signals to produce said another x-deflection signal.

27. An image registration system according to claim 26 wherein said combining circuit means combines said y-reference signal and said modulated y-error signals to produce a first y-summation signal, inverts the polarity of said y-reference signal and combines the resultant complementary y-reference signal and said complementary modulated y-error signals to produce a second y-summation signal, combines said y-reference signal and said complementary modulated y-error signals to produce a third y-summation signal, combines said complementary y-reference signal and said modulated y-error signals to produce a fourth x-summation signal, obtains the difference between said first and second y-summation signals to produce said one y-deflection signal, and obtains the difference between said third and fourth y-summation signals to produce said another y-deflection signal.

28. An image registration system according to claim 27 wherein said modulation means comprises a plurality of modulators each connected to receive one of said analyzed error signals.

29. An image registration system according to claim 28 wherein each of said modulators comprises a dual, matcHed field effect transistor having common drain electrodes connected to receive one of said analyzed error signals.

30. An image registration system according to claim 29 wherein each of said modulators comprise a differential amplifier connected to amplify the dual outputs of said field effect transistor.

31. An image registration system according to claim 30 wherein said reference signal is applied differentially to the gate electrodes of said dual transistors.