INTERPULSE TIME INTERVAL DETECTION CIRCUIT
First Claim
Patent Images
1. In a circuit for providing an indicative output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time, the combination comprising:
- a first flip-flop;
means responsive to the trailing edge of the input signals for setting the first flip-flop;
delay means responsive to the input pulses for producing an output signal a given interval of time after each input pulse for resetting the first flip-flop; and
a second flip-flop connected to be set by an input signal when the first flip-flop is set and to be reset by an input signal if the first flip-flop is reset, for producing the indicative output signal when set.
0 Assignments
0 Petitions
Accused Products
Abstract
Circuit for producing an output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time. The input signals set a flip-flop which is reset by the input pulses delayed by the given interval of time. A second flip-flop producing the output signal is set by the input signals if the first flip-flop is set and is reset if the first flip-flop is reset.
-
Citations
6 Claims
-
1. In a circuit for providing an indicative output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time, the combination comprising:
- a first flip-flop;
means responsive to the trailing edge of the input signals for setting the first flip-flop;
delay means responsive to the input pulses for producing an output signal a given interval of time after each input pulse for resetting the first flip-flop; and
a second flip-flop connected to be set by an input signal when the first flip-flop is set and to be reset by an input signal if the first flip-flop is reset, for producing the indicative output signal when set.
- a first flip-flop;
-
2. The invention as set forth in claim 1 wherein said second-stated means comprises a delay means having a delay interval equal to the time duration of said input signals.
-
3. The invention as set forth in claim 2 wherein said delay means is comprised of the leading edge delay circuit.
-
4. The invention as set forth in claim 3 wherein said first flip-flop is an S-R flip-flop and said second flip-flop is a clocked J-K flip-flop.
-
5. The invention as set forth in claim 4 wherein said second flip-flop is a D-type flip-flop.
-
6. The invention as set forth in claim 5 including a coincidence gate responsive to the input signals and the output of the second flip-flop for producing output signals when input signals occur and the second flip-flop is in the set state.
Specification