OXIDE COATED SEMICONDUCTOR DEVICE HAVING [311] PLANAR FACE

• US 3,636,421 A
• Filed: 12/23/1968
• Issued: 01/18/1972
• Est. Priority Date: 12/28/1967
• Status: Expired due to Term

• Current Assignee: Hisashi Hara, Isao Sasaki, Tai Sato, Yoshiyuki Takeishi
• Original Assignee: Hisashi Hara, Isao Sasaki, Tai Sato, Yoshiyuki Takeishi
• Inventors: Hara, Hisashi, Sasaki, Isao, Takeishi, Yoshiyuki, Sato, Tai
• Primary Examiner(s): Huckert, John W.
• Assistant Examiner(s): Larkins, William D.
• Application Number:
  US04/786,113
• Time in Patent Office: 1,121 Days
• Field of Search: 317/234UA,235B,235AL,235AS
• US Class Current: 257/405
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: Y10S 148/053 Field effect transistors fets
• CPC Class Codes: Y10S 148/072 Heterojunctions
• CPC Class Codes: Y10S 148/115 Orientation

Abstract

A semiconductor device includes a single crystal substrate comprising a flat surface which has a (311) crystal plane with a tolerance of + OR - 2* with respect to said (311) lattice plane. An insulating film is formed on the flat top surface of the substrate.

Claims

2. A semiconductor device according to claim 1 wherein said insulating film covers a portion of said flat top surface, said film being comprised of an oxide of silicon, and further comprising electrodes on said film and on the remaining uncoated portion of said flat top surface.

3. A semiconductor device according to claim 1 wherein the substrate is formed of silicon.

4. A semiconductor device according to claim 3 comprising:

a planar type transistor formed within said substrate and having collector, base and emitter regions formed within said flat top surface of said substrate, first and second PN-junctions being formed between the respective collector and base regions and the base and emitter regions, said PN-junctions extending to said flat top surface;

said insulating film covering at least said PN-junctions at said flat top surface; and

emitter, base and collector electrodes attached to said emitter, base and collector regions, respectively.

5. A semiconductor device according to claim 3 comprising:

a field effect transistor formed within said substrate, said field effect transistor having a respective source and drain region extending from said flat top surface into said substrate, said insulating film comprising a silicon oxide film formed on said flat top surface at least between said source and drain regions; and

electrodes connected to said source and drain regions and to that part of said oxide film between said regions.

6. A semiconductor device according to claim 6 further comprising at least one active region of opposite conductivity type to that of said substrate formed within said substrate and extending from said flat top surface.