DIGITAL FREQUENCY SYNTHESIZER

• US 3,641,442 A
• Filed: 06/25/1970
• Issued: 02/08/1972
• Est. Priority Date: 06/25/1970
• Status: Expired due to Term

• Current Assignee: Robert J. Boucher
• Original Assignee: Robert J. Boucher
• Inventors: Boucher, Robert J.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/049,688
• Time in Patent Office: 593 Days
• Field of Search: 328/37,15,187,14 331/38,40,45,56 324/77B,83D 307/215,218
• US Class Current: 327/105
• CPC Class Codes: H03B 21/00 Generation of oscillations by combining unmodulated signals of different frequencies H03B19/00 takes precedence; frequency changing circuits in general H03D
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03B 28/00 Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in ac-ac converters H02M5/18
• CPC Class Codes: H03C 1/60 with one sideband wholly or partially suppressed
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F

Abstract

A system for generating any frequency in a desired band where, in one embodiment, a phase shifting circuit converts the output signal of a reference oscillator into a plurality of incremental phase shifts which are respectively applied to a plurality of gating circuits. In response to a multibit binary word, adder and register circuits combine to add the multibit binary word to itself at each occurrence of clock pulses and apply the four most significant bits of the sum therefrom to each of the plurality of gating circuits in order to selectively control the operation of the plurality of gating circuits to produce an output signal whose frequency is a function of the amplitude of the multibit binary word.

Claims

1. A frequency synthesizer system comprising:

first oscillator means for developing a sequence of sinusoidal signals;

second oscillator means coupled to said first oscillator means for developing sequences of first and second signals as a function of the sequence of sinusoidal signals applied thereto, the first and second signals being phase coherent with the sinusoidal signals;

phase shift means coupled to said first oscillator means for producing a plurality of sinusoidal phase shift increments in response to the sinusoidal signals;

first means coupled to said second oscillator means for sequentially developing a plurality of multibit numbers in response to the first and second signals; and

gating means having a common output terminal and respectively coupled to said phase shift means and said first means and being responsive to the plurality of multibit numbers therefrom for selectively passing to said common output terminal the plurality of phase shift increments to synthesize a desired output frequency.

2. The system of claim 1 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers;

And a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

3. The system of claim 1 wherein said gating means includes:

a first plurality of gates coupled to said first means for selectively developing enabling signals in response to the plurality of multibit numbers; and

a second plurality of gates respectively coupled to said first plurality of gates and said phase shift means for synthesizing the desired output frequency in response to the enabling signals and the plurality of sinusoidal phase shift increments.

4. The system of claim 3 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to each of said first plurality of gates and to said second storage register for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

5. The system of claim 1 wherein said phase shift means includes a tapped resistor network for producing the plurality of sinusoidal phase shift increments.

6. The system of claim 5 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

7. The system of claim 5 wherein said gating means includes:

a first plurality of gates coupled to said first means for selectively developing enabling signals in response to the plurality of multibit numbers; and

a second plurality of gates respectively coupled to said first plurality of gates and said phase shift means for synthesizing the desired output frequency in response to the enabling signals and the plurality of sinusoidal phase shift increments.

8. The system of claim 7 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

9. The system of claim 8 further including:

a circuit coupled to said gating means for filtering undesirable frequencies from the plurality of phase shift increments being passed.

10. The system of claim 1 further including:

second means coupled between said first oscillator means and said phase shift means for converting the sinusoidal signals into frequency-scaled sinusoidal signals;

said phase shift means being responsive to the frequency-scaled sinusoidal signals for producing the plurality of phase shift increments.

11. The system of claim 10 wherein said phase shift means includes a tapped delay line.

12. The system of claim 11 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage reGister coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

13. The system of claim 11 wherein said gating means includes:

a first plurality of gates coupled to said first means for selectively developing enabling signals in response to the plurality of multibit numbers; and

a second plurality of gates respectively coupled to said first plurality of gates and said phase shift means for synthesizing the desired output frequency in response to the enabling signals and the plurality of frequency-scaled sinusoidal phase shift increments.

14. The system of claim 13 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

15. The system of claim 1 wherein said second oscillator means includes:

a first frequency multiplier coupled to said first oscillator means for frequency multiplying the sinusoidal signal to develop a third signal; and

a clock generator coupled to said frequency multiplier for developing the first and second signals in response to said third signal.

16. The system of claim 1 wherein said second oscillator means includes:

a first frequency divider coupled to said first oscillator means for frequency dividing the sinusoidal signal to develop a fourth signal; and

a clock generator coupled to said frequency divider for developing the first and second signals in response to said fourth signal.

17. The system of claim 1 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

18. The system of claim 1 wherein said gating means includes:

a first plurality of gates coupled to said first means for selectively developing enabling signals in response to the plurality of multibit numbers; and

a second plurality of gates respectively coupled to said first plurality of gates and said phase shift means for synthesizing the desired output frequency in response to the enabling signals and the plurality of sinusoidal phase shift increments.

19. The system of claim 18 wherein said first means includes:

a first storage register for developing a digital frequency command number;

a second storage register coupled to said first storage register and being responsive to each of the second signals and the command number for sequentially developing the plurality of multibit numbers; and

a third storage register coupled to said second storage register and said gating means for sequentially applying the plurality of multibit numbers to said gating means in response to the first signals.

20. The system of claim 19 further including:

a circuit coupled to said gating means for filtering undesirable frequencies from the plurality of sinusoidal phase shift increments being passed.

21. The system of claim 10 wherein:

said second means is a second frequency multiplier for frequency multiplying the sinusoidal signals to develop the frequency-scaled sinusoidal signals.

22. The system of claim 10 wherein:

said second means is a second freQuency divider for frequency dividing the sinusoidal signals to develop the frequency-scaled sinusoidal signals.

23. A frequency synthesizer comprising:

an oscillator for developing a sinusoidal signal;

a phase shifter circuit coupled to said oscillator for phase shifting the sinusoidal signal to produce a plurality of sinusoidal phase shift increments;

a clock generator coupled to said oscillator for generating sequences of first and second signals in response to the sinusoidal signals;

storage means coupled to said clock generator and being responsive to the first and second signals therefrom for sequentially developing a plurality of multibit numbers; and

gating means having a common output terminal and respectively coupled to said phase shifter circuit and said register means and being responsive to the plurality of multibit numbers therefrom for selectively passing to said common output terminal the plurality of sinusoidal phase shift increments to synthesize a desired output frequency.