HIGH-SPEED SAMPLE AND HOLD SIGNAL LEVEL COMPARATOR

• US 3,646,361 A
• Filed: 10/16/1970
• Issued: 02/29/1972
• Est. Priority Date: 10/16/1970
• Status: Expired due to Term

• Current Assignee: Harold J. Pfiffner
• Original Assignee: Harold J. Pfiffner
• Inventors: Pfiffner, Harold J.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US05/081,235
• Time in Patent Office: 501 Days
• Field of Search: 307/235,289,290 328/150,151
• US Class Current: 327/77
• CPC Class Codes: H03K 3/2893 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A sample and hold comparator fabricated with emitter coupled logic using only one transistor-type, resistors, and interconnects and including a differential comparator and logic circuit for comparing an input signal VIN with a reference signal VREF in response to a short duration sample and hold pulse VS/H to produce a digital ONE or ZERO output signal depending upon whether the compared input signal is above or below the reference signal. The differential comparator and logic circuit being further responsive to a regenerative feedback signal produced by a differential amplifier in response to the output signal for latching or holding the state of the sample and hold comparator at the comparison state so that it is not further responsive to variations in the input signal VIN until after a reset pulse VRESET is received by it for clearing the sample and hold comparator circuitry.

Claims

1. A sample and hold comparator comprising:

comparator logic means including a plurality of emitter coupled logic transistors, having a common output circuit, said transistors being selectively coupled to receive at their respective base terminals individual ones of a plurality of input voltages including an input voltage, a reference voltage, a reset voltage, a sample and hold voltage and a feedback voltage, amplifier means coupled to said common output circuit and operable when said sample and hold voltage is applied for producing an output voltage of a first level if said input voltage is less than said reference voltage, and an output voltage of a second level if said input voltage is greater than said reference voltage; and

feedback amplifier means responsive to the level of said output voltage for regeneratively producing said feedback voltage which is operable to maintain said output voltage of said comparatoR logic means.

2. The sample and hold comparator of claim 1 in which said transistors are only operable in their active regions below saturation.

3. The sample and hold comparator of claim 2 in which all of said transistors are of the same transistor type.

4. The sample and hold comparator of claim 1 in which all of said transistors are NPN transistors.

5. The sample and hold comparator of claim 1 which all of said transistors are of the same transistor type.

6. The sample and hold comparator of claim 1 wherein said comparator logic means further includes an emitter coupled logic transistor coupled to receive at a base terminal a reset voltage which overrides the other applied voltages when the reset voltage is at a level that relatively exceeds the level of the other applied voltages to switch the output voltage of said comparator logic means to the first level during the time of the reset voltage, and a second emitter coupled logic transistor coupled to receive at a base terminal a sample and hold voltage which overrides the other applied voltages to switch the output voltage of said comparator logic means to the first level when the sample and hold voltage is at a level that relatively exceeds the level of the other applied voltages.

7. The sample and hold comparator of claim 6 in which two of said plurality of emitter coupled logic transistors of said comparator logic means are operably responsive to the sample and hold voltage so that the greatest relative magnitudes of the input voltage and the reference voltage to selectively turn on one of said emitter coupled logic transistors to produce an output voltage of the first level of the second level respectively.

8. The sample and hold comparator of claim 7 wherein one of said plurality of emitter coupled logic transistors of said comparator logic means is responsive to the feedback voltage such that the reference voltage and the sample and hold voltage are operable to produce the second level output voltage of said comparator logic means when the reference voltage is relatively greater than the input voltage and the input voltage and the feedback voltage are operable to produce the first level output voltage if the input voltage is relatively greater than the reference voltage.

9. The sample and hold comparator of claim 8 in which said comparator logic means includes a plurality of emitter coupled logic transistors coupled as a logical differential amplifier having a first circuit branch with a first, a second, and a third transistor each with their collector terminals and their emitter terminals respectively coupled in common, the base terminals of individual ones of said three transistors being coupled to receive the reset voltage, the sample and hold voltage, and the reference voltage, respectively, and a second circuit branch including a fourth and a fifth emitter coupled logic transistor having their emitter terminals and their collector terminals respectively coupled in common circuit relationship and their base terminals respectively coupled to receive the input voltage and the feedback voltage.

10. The sample and hold comparator of claim 9 in which said feedback amplifier includes a differential amplifier having a first transistor coupled to receive a voltage corresponding to the output voltage at a base terminal and a second transistor coupled to receive a base bias voltage at a base terminal such that said first transistor is turned on and said second transistor is tuned off when the received output voltage is at one of the first and second levels and said second transistor is turned on and said first transistor is turned off when the received output voltage is at the other of the said first level and second level, impedance means coupled to the collector terminal of one of said transistors in said differential amplifier to produce a voltage corresponding to the level of the received input signal, and transistor means coupled to receive the last said voltage to produce a regenerative feedback voltage of a first level having a minimum voltage level relatively greater than the maximum expected input voltage and of a second level having a voltage level relatively less than the maximum expected input voltage level, the first and the second levels of the feedback voltage corresponding to the levels of the output voltages.

11. The sample and hold comparator of claim 10 in which said transistor means coupled to receive the output signal of said feedback amplifier includes means for rereferencing the voltage level of the feedback voltage signal relative to the input voltage range.

12. The sample and hold comparator of claim 10 in which said transistor means coupled to receive the output voltage of said feedback amplifier to produce a feedback voltage includes diode connected transistor means for rereferencing the voltage level of the feedback voltage relative to the input voltage range.

13. The sample and hold comparator of claim 12 further including buffer means including an emitter follower transistor having a base terminal coupled to receive the output voltage of said comparator logic means and an emitter terminal coupled to an emitter follower resistor, and the output voltage being produced by the voltage drop across said emitter follower resistor.

14. The sample and hold comparator of claim 1 wherein two of said plurality of emitter coupled logic transistors of said comparator logic means are operably responsive to the sample and hold voltage so that the greatest relative magnitudes of the input voltage and the reference voltage to selectively turn on one of said emitter coupled logic transistors to produce an output voltage of the first level or the second level respectively.

15. The sample and hold comparator of claim 14 wherein one of said plurality of emitter coupled logic transistors of said comparator logic means is responsive to the feedback voltage such that the reference voltage and the sample and hold voltage is operable to produce the second level output voltage of said comparator logic means when the reference voltage is relatively greater than the input voltage and the input voltage and the feedback voltage are operable to produce the first level output voltage if the input voltage is relatively greater than the reference voltage.

16. The sample and hold comparator of claim 15 in which said feedback amplifier includes a differential amplifier having a first transistor coupled to receive a signal corresponding to the output voltage at a base terminal and a second transistor coupled to receive a base bias voltage at a base terminal such that said first transistor is turned on and said second transistor is turned off when the received output voltage is at one of the first and second levels and said second transistor is turned on and said first transistor is turned off when the received output voltage is at the other of the said first level and second level, impedance means coupled to the collector terminal of one of said transistors in said differential amplifier to produce a voltage corresponding to the level of the received input voltage, and transistor means coupled to receive the last said voltage to produce a regenerative feedback voltage of a first level having a minimum voltage level relatively greater than the maximum expected input voltage and of a second level having a voltage level relatively less than the minimum expected input voltage level, the first and the second levels of the feedback voltages corresponding to the levels of the output voltages.

17. The sample and hold comparator of claim 16 in which said transistor means coupled to receive the output voltage of said feedback amplifier includes means for rereferencing the voltage level of the feedback voltage relative to the input voltage range.

18. The sample and hold comparator of claim 16 in which said transistor means coupled to receive the output voltage of said feedback amplifier to produce a feedback voltage includes diodE connected transistor means for rereferencing the voltage level of the feedback voltage relative to the input voltage range.