SWITCH CODING CIRCUITRY

• US 3,651,463 A
• Filed: 04/17/1970
• Issued: 03/21/1972
• Est. Priority Date: 04/17/1970
• Status: Expired due to Term

• Current Assignee: Edward B. Rawson, John B. Dowling
• Original Assignee: Edward B. Rawson, John B. Dowling
• Inventors: Rawson, Edward B., Dowling, John B.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/029,422
• Time in Patent Office: 704 Days
• Field of Search: 340/147,345,166 178/17,26,79
• US Class Current: 341/26
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence

Abstract

Switch coding circuitry common to a plurality of mechanically unrelated input switches and operative to provide detection of a valid switch actuation and to provide a digital representation of the identity of an actuated switch.

Claims

1. Switch coding circuitry operative to provide a binary coded indication of the actuation of one switch amongst a plurality of switches, said system comprising:

a multiplexer receiving a plurality of inputs each containing a signal representative of the condition of one switch in said plurality of switches, and operative in response to interrogation by a binary signal to provide an output signal indicative of the condition of the one of said plurality of switches corresponding to the binary signal;

counter means operative to cycle through a plurality of binary states and providing said binary signal to said multiplexer as a signal representative of the binary state of said counter means;

sensor means for detecting an actuation output signal from said multiplexer indicative of an actuated condition of one of said plurality of switches;

timing means operative in response to said actuation output signal from said multiplexer for generating a gate timing interval;

said sensor means being operative in response to said gate timing interval signal to provide a sensor output signal in response to detection of an actuation output signal after the elapse of said gate timing interval, said sensor output signal being representative of a valid switch actuation; and

means operative in response to said sensor output signal for inhibiting cycling of said counter means, the binary state at which said counter means is inhibited being said binary coded representation identifying the actuated switch of said plurality of switches.

2. Circuitry according to claim 1 wherein said multiplexer includes a plurality of first multiplexer gates each having a plurality of input terminals, an output terminal and multi-bit control terminals, each of said input terminals adapted to be connected to a respective switch;

a second multiplexer gate having a plurality of input terminals each connected to a respective output terminal of said first multiplexer gates, an output terminal connected to said sensor mEans and multi-bit control terminals;

the control terminals of said first multiplexer gates each being connected to the least significant bits of said counter output, the control terminals of said second multiplexer gate being connected to the most significant bits of said counter output.

3. Circuitry according to claim 2 wherein said timing means includes clock means for providing clock signals;

bistable gate means operative in response to the output signal from said second multiplexer gate to change its output condition; and

an AND gate having an input coupled to the output of said bistable gate means, a second input coupled to said clock means and an output coupled to said timing means;

said AND gate being operative to remove clock pulses from said timing means in the presence of an output signal from said second multiplexer gate thereby to initiate said timing gate.

4. Circuitry according to claim 3 including control means for producing an interrupt signal upon the occurrence of an output signal from said sensor means.

5. Circuitry according to claim 3 including control means for producing an interrupt signal upon the occurrence of an output signal from said sensor means, and for resetting said circuitry upon receipt of a reset signal.

6. Circuitry according to claim 3 wherein said clock means provides first clock pulses to said AND gate, and second clock pulses phase shifted by 180* from said first clock pulses to said gate means.

7. The system of claim 1 further including means for causing said timer means to reinitiate said gate timing interval signal intermediate of each count of said counter.