TRAFFIC SIGNAL CONTROL SYSTEM

• US 3,652,983 A
• Filed: 02/11/1970
• Issued: 03/28/1972
• Est. Priority Date: 02/21/1969
• Status: Expired due to Term

• Current Assignee: Mituhisa Hosika, Tadao Endo
• Original Assignee: Mituhisa Hosika, Tadao Endo
• Inventors: Hosika, Mituhisa, Endo, Tadao
• Primary Examiner(s): Cooper, William C.
• Application Number:
  US05/010,403
• Time in Patent Office: 776 Days
• Field of Search: 340/35
• US Class Current: 340/913
• CPC Class Codes: G08G 1/081 Plural intersections under common control

Abstract

A system for controlling the traffic signals within a relatively wide district divided into a plurality of subdistricts, in each of which there are distributed many traffic signals at different places. A submaster controller coordinately controls many local controllers within each subdistrict, and a master controller controls all the submaster controllers within the wide district. The master controller gives the same cycle pulses and the same series of synchronizing pulses, but different offsets, to different submaster controllers, and each submaster controller provides a second series of synchronizing pulses, which are displaced in time from the first series of synchronizing pulses by the offset time given to the submaster controller, to the local controllers belonging to the submaster controller, so that the local controllers control their respective traffic signals on the basis of the synchronizing pulses received from the submaster controller. Thus, with proper different offsets given to the different submaster controllers, all the traffic signals in the wide district are coordinately controlled in accordance with the actual traffic conditions in the different subdistricts for establishment of smooth traffic flows throughout the wide district.

Claims

1. A system for controlling the traffic signals within a wide district divided into a plurality of subdistricts, comprising:

a plurality of local controllers to control the traffic signals proVided at different places in each of said subdistricts, a submaster controller provided for each of said subdistricts for controlling said local controllers within each said subdistrict; and

a single master controller for controlling said submaster controllers and including means for providing cycle pulses and a first series of synchronizing pulses to be applied to all said submaster controllers and means for providing a different offset signal to be applied to each of said submaster controllers;

each said submaster controller includ-ing means for providing a second series of synchronizing pulses displaced from said firstmentioned series of synchronizing pulses by the offset time as determined by said offset signal, and means for applying said second series of synchronizing pulses to each said local controller, whereby each said local controller controls the traffic signals belonging thereto on the basis of said second series of synchronizing pulses received from each said submaster controller.

2. The system of claim 1, wherein each said submaster controller includes a register for storing said offset signal received from said master controller, a counter for counting said cycle pulses received from said master controller to produce said second series of synchronizing pulses as predetermined counts are reached, and circuit means for controlling said counter so that the time between the occurrence of said first and second series of synchronizing pulses becomes equal to said offset stored in said register.

3. The system of claim 1, wherein said submaster controller comprises a register for storing said offset signal, a counter for counting said cycle pulses to produce said second series of synchronizing pulses as predetermined counts are reached, a coincidence circuit operable to produce an output when the count on said counter has come to coincide with said offset stored in said register, means for detecting a discrepancy in occurrence between said output from said coincidence circuit and a first pulse in said first series of synchronizing pulses to produce an output, and means operable in response to said output from said detecting means to change the frequency of said cycle pulses to be applied to said counter.

4. The system of claim 1, wherein each said submaster controller comprises a first counter for counting said cycle pulses, a register for storing said offset signal, said register also receiving said cycle pulses to function as a second counter having the same counting capacity as said first counter to produce a signal when a predetermined count has been reached, means for detecting a discrepancy in occurrence between said signal from said second counter and a first pulse in said first series of synchronizing pulses to produce an output, and means operable in response to said last-mentioned output to change the frequency of said cycle pulses to be applied to said first counter.