CODE COMMUNICATION FRAME SYNCHRONIZATION SYSTEM

• US 3,654,492 A
• Filed: 08/24/1970
• Issued: 04/04/1972
• Est. Priority Date: 08/24/1970
• Status: Expired due to Term

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: James M. Clark
• Inventors: Clark, James M.
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/066,520
• Time in Patent Office: 589 Days
• Field of Search: 307/208,209,210,269 328/63,72 178/66,69.5R 325/30,38A 340/347R
• US Class Current: 327/141
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Abstract

Logic circuitry converts binary intelligence into a first amplitude for a binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' and a second amplitude for a binary '"'"''"'"''"'"''"'"'O.'"'"''"'"''"'"''"'"' This same logic circuitry converts a frame timing signal into a third amplitude half way between the first and second amplitudes. These three amplitudes are converted into, for instance, three distinct frequencies with the frequency corresponding to the third amplitude being disposed half way between the frequencies corresponding to the first and second amplitudes. After transmission, the three amplitudes are recovered. A first voltage comparator having a reference voltage equal to the third amplitude recovers the binary intelligence from which a local clock is generated with the local clock pulses being delayed to be centered in the binary digits. A pair of voltage comparators having reference voltages straddling the third amplitude, but less than the first amplitude and greater than the second amplitude and a sampling gate responding to the outputs of the pair of voltage comparators and the local clock pulses recover the frame timing signal to enable frame synchronization of the receiver with the transmitter.

Claims

1. Binary intelligence communication apparatus comprising:

a first source of binary intelligence signal including binary bits each having a given width occurring at a given bit rate;

a second source of frame timing signal defining binary frame periods, each of said frame periods including a plurality of said binary bits;

first means coupled to said first and second source responsive to said binary signal to convert one binary condition thereof to a first given amplitude having a width equal to said given width and the other binary condition thereof to a second given amplitude having a width equal to said given width, said second amplitude being different than said first amplitude and responsive to said frame timing signal to provide a frame synchronization signal having a third given amplitude intermediate said first and second amplitudes, a width equal to said given width and occupying the position of a given one of said binary bits during each of said frame periods; and

secOnd means coupled to said first means to provide a third signal for transmission having a predetermined characteristic thereof varied in a given manner to represent said first, second and third amplitudes.

2. Apparatus according to claim 1, wherein said third amplitude is half way between said first and second amplitudes.

3. Apparatus according to claim 1, wherein said second means includes third means responsive to said first amplitude to generate a signal having a first frequency, responsive to said second amplitude to generate a signal having a second frequency different than said first frequency, and responsive to said third amplitude to generate a signal having a third frequency intermediate said first and second frequencies.

4. Apparatus according to claim 3, wherein said third amplitude is half way between said first and second amplitudes, and said third frequency is half way between said first and second frequencies.

5. Apparatus according to claim 3, wherein said third means includes a voltage controlled oscillator.

6. Apparatus according to claim 1, wherein said first means includes logic circuit means.

7. Apparatus according to claim 6, wherein said logic circuit means includes first flip flop means, second flip flop means, logic components coupled between said first and second sources and said first and second flip flop means for control thereof, and two equal valued resistors coupled in series between the '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' outputs of said first and second flip flop means, the junction of said resistors providing said first, second and third amplitudes to control said second means.

8. Apparatus according to claim 6, wherein said logic circuit means includes a first flip flop, a second flip flop, an INHIBIT gate having its normal input coupled to said first source, its inhibit input coupled to said second source and its output coupled to the set input of said first flip flop, a first NOT gate coupled between the output of said INHIBIT gate and the reset input of said first flip flop, an OR gate having one input coupled to said first source the other input coupled to said second source and its output coupled to the set input of said second flip flop, a second NOT gate coupled between the output of said OR gate and the reset input of said second flip flop, and two equal valued resistors coupled in series between the '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' outputs of said first and second flip flops, the junction of said resistors providing said first, second and third amplitudes to control said second means.

9. Apparatus according to claim 1, further including third means coupled to said second means to demodulate said third signal and recover said first, second and third amplitudes;

fourth means coupled to said third means to recover said binary signal form said demodulated third signal; and

fifth means coupled to said third means to recover said synchronization signal when the amplitude of said demodulated third signal is less than a fourth amplitude and greater than a fifth amplitude, said fourth amplitude being less than said first amplitude but greater than said third amplitude and said fifth amplitude being greater than said second amplitude but less than said third amplitude.

10. Apparatus according to claim 9, wherein said fourth means includes a first bias source providing a first voltage equal to said third amplitude, a first voltage comparator coupled to said third means and said first bias source to recover said binary signal, and sixth means coupled to the output of said first comparator to extract a clock signal from said recovered binary signal having said given bit rate, said clock signal being time displaced with respect to the transitions of said recovered binary signal;

and said fifth means includes a second bias source providing a second voltage having an amplitude less than said first amplitude but greater than said third amplitude, a third bias source providing a third voltage having an amplitude greater than said second amplitude but less than said third amplitude, a second voltage comparator coupled to said third means and said second bias source, a third voltage comparator coupled to said third means and said third bias source, and coincident gate means coupled to the output of each of said second and third comparators and said sixth means to recover said synchronization signal.

11. Apparatus according to claim 1, wherein said first means includes a first flip flop, a second flip flop, an INHIBIT gate having its normal input coupled to said first source, its inhibit input coupled to said second source and its output coupled to the set input of said first flip flop, a first NOT gate coupled between the output of said INHIBIT gate and the reset input of said first flip flop, an OR gate having one input coupled to said first source, the other input coupled to said second source and its output coupled to the set input of said second flip flop, a second NOT gate coupled between the output of said OR gate and the reset input of said second flip flop, and two equal valued resistors coupled in series between the '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' outputs of said first and second flip flops, the junction of said resistors providing said first, second and third amplitudes to control said second means;

and further including third means coupled to said second means to demodulate said third signal and recover said first, second and third amplitudes;

a first bias source providing a first voltage equal to said third amplitude;

a first voltage comparator coupled to said third means and said first bias source to recover said binary signal;

sixth means coupled to the output of said first comparator to extract a clock signal from said recovered binary signal, said clock signal being time displaced with respect to the transitions of said binary signal;

a second bias source providing a second voltage having an amplitude less than said first amplitude but greater than said third amplitude;

a third bias source providing a third voltage having an amplitude greater than said second amplitude but less than said third amplitude;

a second voltage comparator coupled to said third means and said second bias source;

a third voltage comparator coupled to said third means and said third bias source; and

coincident gate means coupled to the output of each of said second and third comparators and said sixth means to recover said synchronization signal.