USE OF FAULTY STORAGE CIRCUITS BY POSITION CODING

• US 3,654,610 A
• Filed: 09/28/1970
• Issued: 04/04/1972
• Est. Priority Date: 09/28/1970
• Status: Expired due to Term

• Current Assignee: Frank S. Greene Jr, Wendell B. Sander
• Original Assignee: Frank S. Greene Jr, Wendell B. Sander
• Inventors: Sander, Wendell B., Greene, Frank S. Jr.
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/076,056
• Time in Patent Office: 554 Days
• Field of Search: 340/172.5,347DD,174ED 235/153
• US Class Current: 365/49.1
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory system having an array of a predetermined number of storage cells, each for storing a single bit of binary information, arranged in rows and columns, the rows and columns each having binary addresses, the system including at least one redundant row of storage cells and one or more defective rows, or at least one redundant column of storage cells and one or more defective columns, or both. The contained cells of the redundant rows or columns are not required to make up the required number of storage cells. A code converter is embodied for converting the binary addresses of each of the rows and columns of the system to combinatorial addresses, each combinatorial address being associated with a row or column of the array, the maximum number of combinatorial addresses to which the binary addresses of all the rows or all the columns may be converted being at least one more than the maximum number of binary addresses of all the rows or all the columns, there being no binary address associated with the additional combinatorial addresses. A connection mechanism is included for connecting the code converter to the array of storage cells, the connection providing that the additional combinatorial addresses are associated with the defective rows or columns, and the combinatorial addresses with which the binary addresses of the defective rows or columns would normally be associated are associated with the redundant rows or columns.

Claims

1. A memory system having an array of a predetermined number of storage cells, each for storing a single bit of binary information, arranged in orthogonal lines, the lines each having binary addresses, comprising:

at least one redundant line of storage cells and one or more defective lines in the same direction as the redundant line, the contained cells of said redundant lines not being required to make up said predetermined number of storage cells and the number of redundant lines being at least equal to the number of defective lines;

a code converter permanently connected to electrically convert the binary addresses for each of the lines of the system to combinatorial addresses, each combinatorial address being associated with a line of the array, the maximum number of combinatorial addresses to which the binary addresses of all the lines may be converted being at least one more than the maximum number of binary addresses of all the lines in the same direction, there being no binary address associated with the additional combinatorial addresses; and

means selectively connecting said code converter to said array of storage cells, and selective connection providing that said additional combinatorial addresses are associated with said defective lines, and the combinatorial addresses with which the binary addresses of the defective lines would normally be associated are associated with the redundant lines.

2. The memory system of claim 1 further characterized by said memory array being fabricated in monolithic chips of semiconductor material.

3. The memory system of claim 2 further characterized by said predetermined number of cells being in one single monolithic chip of semiconductor material and said redundant rows or columns of cells being in one or more different chips.

4. The memory system of claim 1 further characterized by said memory array being fabricated in a single monolithic chip of semiconductor material.

5. The memory system of claim 1 further characterized by the array having 256 binary bits and at least one redundant line.

6. The memory system of claim 1 further characterized by the array having 256 binary bits and at least one redundant line in one orthogonal direction and one in the opposite direction.