DATA DEMODULATOR EMPLOYING COMPARISON

• US 3,656,064 A
• Filed: 09/17/1969
• Issued: 04/11/1972
• Est. Priority Date: 09/17/1969
• Status: Expired due to Term

• Current Assignee: Donald G. Shuda, George R. Giles
• Original Assignee: Donald G. Shuda, George R. Giles
• Inventors: Giles, George R., Shuda, Donald G.
• Primary Examiner(s): Brody, Alfred L.
• Application Number:
  US04/858,627
• Time in Patent Office: 937 Days
• Field of Search: 329/104,126,145 325/320 178/66 328/151,136,137,138,48
• US Class Current: 329/303
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/1563 using transition or level detection

Abstract

Data demodulator which demodulates a received signal by means of comparing the received signal with itself delayed to produce a comparison signal having one amplitude value upon identity and another different amplitude value upon non-identity. The comparison is performed by a modulo two net-work herein illustrated as an EXCLUSIVE OR gate. The comparison signal is filtered by a digital filter which includes an UP/DOWN counter and associated control circuitry. The output of the digital filter is sampled by a JK flip-flop to provide the demodulated data signal.

Claims

1. A demodulator for detecting first and second digital values of a modulating data signal from a carrier signal which is modulated to have first and second frequencies f1 and f2 corresponding to the first and second digital values, respectively where f1 <

f2;

means for delaying said modulated carrier signal relative to itself by an amount TD which falls between the half period of f2 and the period of f2;

a comparator for operating on the identity and non-identity of said modulated signal and the delayed version thereof to produce a comparison signal having first and second amplitude values upon identity and non-identity, respectively;

a digital filter including (1) counting means selectively enabled to count in first and second directions in response to the first and second levels of said comparison signal and (2) control circuitry for inhibiting the counter from counting beyond first and second counter states and for enabling the counter to count from one of said counter states toward the other upon the occurrence of transitions between the levels of the comparison signal, whereby the output of said counter provides an indication of the modulating data signal.

2. The invention according to claim 1 and further including sampling means for sampling said indication to produce a signal having different amplitude levels corresponding to the first and second digital values.

3. The invention according to claim 2 wherein said digital filter further includes a source of signals to be counted coupled to said counting means by a gating circuit;

and wherein said control circuit is responsive to said comparison signal and to the first and second counter states for (1) enabling the gating circuit in response to each transition of the comparison signal and (2) inhibiting the gating circuit whenever either of the counter states is reached.

4. The invention according to claim 3 wherein said comparison signal includes fallback intervals upon the occurrence of changes in frequency of said modulating signal such that one transition of a pair of transitions defining such a fallback interval occurs before the counter counts from either of said states to the other;

and wherein said control circuitry includes further means for coupling to said gating network from said source signals of a relatively high frequency whenever said counter begins to count from either of said states toward the other and signals of a relatively lower frequency during said fallback intervals.

5. A demodulator for detecting first and second digital values of a modulating data signal from a carrier signal which has been modulated by said data signal;

said demodulator comprising;

means for comparing said modulated carrier signal with a delayed version of itself to provide a comparison signal having first and second amplitude values upon identity and non-identity, respectively; and

a digital filter for filtering said comparison signal to provide an indication of the modulating information, said filter including digital counting means enabled to count in first and second directions in response to the first and second values, respectively, of said comparison signal, whereby the count value of the counting means represents said indication of the modulating information.

6. The invention according to claim 5 wherein said comparison signal represents the modulo two sum of the modulated carrier signal and the delayed version thereof.

7. The invention according to claim 6, and further including means for converting said filter provided indication to a demodulated signal indicative of the modulating data signal.

8. The invention according to claim 7 wherein said digital filter further includes a source of signals to be counted coupled to said counter by a gating circuit and a control circuit responsive to said comparison signal and to first and second counter states for (1) enabling said gating circuit in response to each transition of the comparison signal and (2) inhibiting said gating circuit whenever either of said counter states is reached.

9. The invention according to claim 8 wherein said carrier signal is modulated to have first and second frequencies corresponding to the first and second digital values, respectively, wherein said comparison signal includes fallback intervals upon the occurrence of changes in frequency of said modulating signal such that one transition of a pair of transitions defining such a fallback interval occurs before the counter counts from either of said states to the other, and wherein said control circuitry includes further means for coupling to said gating network from said source signals of a relatively high frequency whenever said counter begins to count from either of said states toward the other and signals of a relatively lower frequency during said fallback intervals.

10. The invention according to claim 2 wherein said comparison means includes modulo two addition means responsive to said modulated signal and the delayed version thereof to provide the modulo two sum thereof, the modulo two sum corresponding to said comparison signal.

11. The invention according to claim 10 wherein said comparison signal includes fallback intervals upon the occurrence of changes in frequency of said modulated signal, such that one transition of a pair of transitions defining such a fallback interval occurs before the counter counts from either of said states to the other, and wherein said control circuitry includes further means for causing said counter to count at a first rate whenever the counter begins counting from either of the states to the other And at a second lower rate during said fallback intervals.

12. The invention according to claim 11 wherein TD is three-fourths of the mean frequency of said first and second frequencies.