PLATINUM THIN-FILM METALLIZATION METHOD

• US 3,657,029 A
• Filed: 12/31/1968
• Issued: 04/18/1972
• Est. Priority Date: 12/31/1968
• Status: Expired due to Term

• Current Assignee: Clyde R. Fuller
• Original Assignee: Clyde R. Fuller
• Inventors: Fuller, Clyde R.
• Application Number:
  US04/788,187
• Time in Patent Office: 1,204 Days
• US Class Current: 438/625
• CPC Class Codes: C23F 1/02 Local etching
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Abstract

Platinum thin-film metallization is selectively etched with aqua regia, using a chromium or titanium film as an etch-resistant mask. In a specific embodiment, an integrated circuit structure is metallized with successive layers of titanium, platinum, gold and a metal selected from molybdenum, tungsten, rhenium and corrosion-resistant alloys thereof. The system is particularly suited for the formation of insulated '"'"''"'"''"'"''"'"'cross-over'"'"''"'"''"'"''"'"' metallization, or multi-level interconnecting metallization.

Claims

2. A method as defined by claim 1 wherein the platinum-palladium group metal is platinum.

3. A method as defined by claim 2 wherein the deposited masking layer is chromium.

4. The method defined in claim 3 wherein the chromium layer is selectively etched with an etchant solution comprising ceric sulfate, sulfuric acid and nitric acid.

5. A method as defined by claim 3 wherein said refractory metal is molybdenum.

6. A method as defined by claim 5 wherein said second insulation layer is silicon oxide.

7. A method as defined by claim 6 wherein said metal layer on said windowed second insulation layer is chromium or titanium.

8. A method as defined by claim 6 wherein said metal layer on said windowed second insulation layer is comprised of successive layers of titanium, platinum and gold.

9. A method for metallizing a semiconductor structure having a first insulation layer on a surface thereof, said first insulation layer having openings therein exposing the semiconductor surface, comprising:

a. sequentially forming a first layer of titanium and then a layer of a metal selected from the platinum-palladium group over the insulation layer, then forming a layer of chromium or a second layer of titanium on the metal of the platinum-palladium group;

b. selectively removing the chromium or second titanium layer to define a desired pattern therein;

c. selecTively removing the platinum-palladium group layer from the regions defined by said pattern;

d. removing the chromium or second titanium layer;

e. selectively removing the first titanium layer from the regions defined by said pattern;

f. sequentially forming a layer of gold and then a layer of a refractory metal over the platinum-palladium group layer; and

g. selectively removing the gold and refractory metal layers from the regions defined by said pattern.

10. The method of claim 9 further comprising forming a second insulation layer over the metal layers, selectively removing the second insulation layer from the regions defined by said pattern, and forming a metal layer over said insulation layer.