REPETITIVE SAMPLING WEIGHTED FUNCTION CONVERTER

• US 3,659,086 A
• Filed: 06/08/1970
• Issued: 04/25/1972
• Est. Priority Date: 06/11/1969
• Status: Expired due to Term

• Current Assignee: Eric Metcalf
• Original Assignee: Eric Metcalf
• Inventors: Metcalf, Eric
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/044,078
• Time in Patent Office: 687 Days
• Field of Search: 235/181,183,160,164,175 340/347AD,347SH 333/18 328/151
• US Class Current: 708/6
• CPC Class Codes: G01R 19/255 using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

An electrical signal is sampled repeatedly and the samples are integrated in analog or digital form to effect active filtering of the signal. Preferably the samples are weighted differently or the inter-sample interval is varied in accordance with a weighting function chosen to improve noise rejection at one or more frequencies.

Claims

1. Apparatus comprising means for receiving an input analog signal;

a sample clock for producing pulses;

converter means responsive to each pulse produced by said sample clock to repetitively sample said input analog signal and to produce a sequence of digital output signals representative of said samples;

first counter means for counting the number of pulses produced by said sample clock and for generating a signal terminating the sequential sampling of said input signal at a preselected count;

means for accumulating the sequence from digital outputs of said converter means; and

logic circuit means for supplying preselected ones of said sequence of digital output signals to said means for accumulating more than once to effect multiplication thereof, the choice of said preselected ones of said sequence and of the effective multiplication constituting a weighting function chosen to improve rejection of specific noise characteristics.

2. Apparatus according to claim 1 wherein said converter means comprises an A/D converter including a second counter means for holding the digital output of said converter, and said logic circuit means includes gate circuit means responsive to selected states of said counter means for supplying the output of said second counter means to said accumulator a predetermined number of times.

3. An analog to digital converter for converting an analog signal, which can include an undesirable noise signal of period T, to a corresponding digital output signal, comprising the combination of conversion means for converting the analog signal to an intermediate digital signal;

timing means for causing said conversion means to produce at least 10 uniformly temporally spaced intermediate digital signals in each interval of time nT, where n is an integer;

means for accumulating said intermediate digital signals to integrate them over the interval nT; and

means for altering the scaling of the values of selected ones of said intermediate digital signals by predetermined factors to substantially reject the undesirable noise signal.