FLEXIBLE COMPUTER ACCESSED TELEMETRY

• US 3,665,417 A
• Filed: 02/19/1971
• Issued: 05/23/1972
• Est. Priority Date: 02/19/1971
• Status: Expired due to Term

• Current Assignee: Edward E. Hilbert, Low George M Deputy Administrator of The National Aeronautics and Space, N/a,, Richard A. Easton
• Original Assignee: Edward E. Hilbert, Low George M Deputy Administrator of The National Aeronautics and Space, N/a,, Richard A. Easton
• Inventors: Hilbert, Edward E., Easton, Richard A., Low, George M. Acting Administrator of the National Aeronautics and Space, N/a,
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Rhoads, Jan E.
• Application Number:
  US05/116,786
• Time in Patent Office: 459 Days
• Field of Search: 340/172.5,150 178/50,69.5 179/15BV
• US Class Current: 713/502
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal

Abstract

Flexible, computer-accessed telemetry is provided by a sequence control unit, auxiliary memory and system control registers to permit sensors and digital data sources to be sampled in a programmed format with various groups of samples taken at different rates. Each programmed sample may be processed for transmission in a specified way by including an operation code with the programmed address code used to select the designated sensor or digital data source. Index registers and a scratch pad memory permit flexibility in programming sample sequencing formats. A particular format may be started, stopped and altered by ground station commands received through a receiver, or directly by a digital computer.

Claims

1. A programmable telemetry system comprising a memory unit having a plurality of randomly accessible memory locations for storing digital signals representing control words for sampling predetermined sources of data at different rates in a desired format, digital signals representing identification codes of said data sources, and digital signals representing the number of data sources to be sampled in sequence at a given rate, a first register coupled to said memory unit for receiving data identification code words in rate groups from predetermined memory locations, all groups except one consisting of a plurality of data sources to be sampled at a desired rate, R/2n where n is a positive integer, relative to said one group which is to be sampled cyclically at a rate R, each group being stored in a unique block of memory locations, a second register coupled to said memory unit for receiving control words in a predetermined order, each control word specifying the memory location of the first data identification code word of a unique rate group, a delay counter coupled to said memory unit for receiving digital signals representing a delay word in the form of a number specifying the number of data sources of a given rate group to be sampled in sequence during one minor frame cycle, where a minor frame is defined as the interval between samples of a given data source occurring once in the highest rate group, and for counting the number of successive samples taken from a given rate group, and sequence control means for loading control words into said second register one at a time from a predetermined block of memory locations, for loading delay words into said counter, one delay word for each control word from a predetermined group of memory locations, for loading data identification control words into said first register from memory locations specified by the control word in said second register, each time incrementing both said control word in said second register and said delay word in said delay counter, for storing each incremented control word within another predetermined block at a memory location uniquely associated with the rate group controlled by the incremented control word being stored when the number of samples specified by said delay word have been taken, and for loading a given control word into said second register from either said predetermined block of memory locations reserved for unincremented control words or from said block reserved for for incremented control words depending upon whether all of the samples from the rate groups controlled have just been completed during the previous minor frame cycle.

2. The combination defined by claim 1 wherein each unincremented control word loaded into said second register includes a flag indicating whether or not the rate group controlled thereby is the last rate group of a minor frame cycle, and said flag is stored with each incremented control word in said memory location uniquely associated with the rate group, each rate group R/2n is identified by the number n representing the exponent of 2 by which the highest rate is divided to determine its group rate, and said sequence control unit includes a third register, means for loading into said third register said number n associated with the rate group being controlled by the control word in said second register, frame counting means for counting in binary form the number of times said flag, loaded into said second register with a control word, indicates that the rate group controlled thereby is the last of a minor frame, means responsive to said number n in said third register for generating a frame return flag when the n least significant binary digits are each equal to zero, and means responsive to said frame return flag for causing the control word for a given group to be loaded from a memory location reserved for an unincremented control word for the group of the group rate associated with the number n, and for causing an unincremented control word for the group of the highest group rate R to always be loaded from a memory location reserved for an unincremented control word.

3. The combination defined by claim 2 wherein which of said predetermined group of memory locations for unincremented control words is, in each instance, selected from a group of n memory locations, where the addresses for the locations in the two groups is comprised in the least significant parts of the numbers 0 to n, such that memory locations 0 to n are reserved for the respective rate groups R, R/21, . . . ,R/2n.

4. The combination defined by claim 3 wherein each delay word for a given rate group is read from a memory location in a unique block of n memory locations, each location of said block is identified by the number n in the least significant portion of its address, and the number n identifying the rate group to be sampled next is read from the same memory location as said delay word for the current rate group to be sampled, and at the same time, including a fourth register into which said number n is read while said delay word is being entered into said delay counter, and means for transferring the content of said fourth register to said third register when said delay counter has counted a number of samples specified by said delay word.

5. The combination defined by claim 4 including a source of system clock pulses, a cyclic timing means connected to said source of clock pulses and responsive thereto for generating a cyclical sequence of step control signals, and wherein said sequence control means responds to said step control signals to transfer the content of said fourth register to said third register during the first step, to load said second register from a memory location specified by the content of said third register and said frame return flag during the second step, to load said delay counter and said fourth register from a memory location specified by said third register during the third step, to load said first register from a memory location specified by said second register during the fourth step, to increment said delay counter if the delay count is not complete, to increment said second register and select the data source specified by said first register during said fifth step, and, if, during the sixth step the number of samples specified by said delay count has been taken, to increment said frame counting means if said flag loaded into said second register with a control word during the second step indicates that the rate group controlled thereby is the last of a minor frame, and to store the incremented control word in a memory location specified by said third register;

otherwise, if the number of samples has not been taken, to recycle to the fourth step from the fifth step.

6. The combination defined by claim 5 wherein said sequence control means recycles to the fourth step from the fifth step through idle sixth, first, second and third steps in order to allow the same amount of time for processing each sample.

7. The combination defined by claim 6 wherein there is at least one additional idle step following each sixth step to allow sufficient time for processing of sampled data.

8. The combination defined by claim 7 wherein each data identification code includes a repeat flag code which, when set to a predetermined value, indicates that the sample specified be taken repeatedly during successive sequencing cycles until the number of samples specified by said delay word for a given rate group has been taken, and wherein the step of incrementing said second register is conditioned on said repeat flag code of a given data identification code not being set to said predetermined value.

9. The combination defined by claim 1 wherein each data identification code word includes a flag code which, when at a predetermined value, indicates the same data identification code word is to be used again, and said sequence control means includes means for inhibiting said control word in said second register from being incremented, whereby the same data identification code word is used for successive samples until the number of samples specified by said delay word has been taken.

10. A programmable telemetry system comprising a memory unit having a plurality of randomly accessible memory locations for storing digital signals representing control words for sampling predetermined sources of data at different rates in a desired format, digital signals representing identification codes of said data sources, and digital signals representing the number of data sources to be sampled in sequence at a given rate, a first register coupled to said memory unit for receiving data identification code words in rate groups from predetermined memory locations, all groups except one consisting of plurality of data sources to be sampled at a desired rate, R/2n where n is a positive integer, relative to said one group which is to be sampled cyclically at a rate R, each group being stored in a unique block of memory locations, a second register coupled to said memory unit for receiving control words in a predetermined order, each control word specifying the memory location of the first data identification code word of a unique rate group, and sequence control means for loading a control words into said second register from a predetermined block of memory locations, loading data identification control words into said first register from memory locations specified by the control word in said second register, each time incrementing said control word in said second register, storing each incremented control word within another predetermined block at a memory location uniquely associated with the rate group controlled by the incremented control word being stored and loading a given control word into said second register from either said predetermined block of memory locations reserved for unincremented control words or from said block reserved for for incremented control words depending upon whether all of the samples from the rate groups have just been completed during the previous minor frame cycle, where a minor frame is defined as the interval between samples of a given data source occurring once in the highest rate group.

11. The combination defined in claim 10 wherein each unincremented control word loaded into said second register includes a flag indicating whether or not the rate group controlled thereby is the last rate group of a minor frame cycle, and said flag is stored with each incremented control word in said memory location uniquely associated with the rate group, each rate group R/2n is identified by the number n representing the exponent of 2 by which the highest rate is divided to determine its group rate, and said sequence control unit includes a third register, means for loading into said third register said number n associated with the rate group being controlled by the control word in said second register, frame counting means for counting in binary form the number of times said flag, loaded into said second register with a control word, indicates that the rate group controlled thereby is the last of a minor frame, means responsive to said number n in said third register for generating a frame return flag when the n least significant binary digits are each equal to zero, and means responsive to said frame return flag for causing the control word for a given group to be loaded from a memory location reserved for an unicremented control word for the group of the group rate associated with the number n, and for causing an unincremented control word for the group of the highest group rate R to always be loaded from a memory location reserved for an unincremented control word.

12. The combination defined in claim 11 wherein which of said predetermined group of memory locations for unincremented control words is, in each instance, selected from a group of n memory locations, where the addresses for the locations in the two groups is comprised in the least significant parts of the numbers 0 to n, such that memory locations 0 to n are reserved for the respective rate groups R, R/21, . . . ,R/2n.