TRANSPONDER MONITORING SYSTEM

• US 3,670,303 A
• Filed: 08/28/1970
• Issued: 06/13/1972
• Est. Priority Date: 08/28/1970
• Status: Expired due to Term

• Current Assignee: John S. Dame
• Original Assignee: John S. Dame
• Inventors: Dame, John S.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/067,875
• Time in Patent Office: 655 Days
• Field of Search: 340/146.1,163,147C,408,47,150
• US Class Current: 714/819
• CPC Class Codes: B61L 25/04 Indicating or recording train identities
• CPC Class Codes: B61L 27/40 Handling position reports or trackside vehicle data
• CPC Class Codes: B61L 27/57 for vehicles or trains, e.g. trackside supervision of train conditions

Abstract

A transponder monitoring system includes a fixed location interrogation station and transponder units carried by vehicles, with the transponder units being placed in an activated transmit mode in response to interrogation pulses transmitted by the interrogation station. The messages received at the interrogation station are verified by the transmission of verification pulses on a bit by bit basis, with failure of verification causing a vehicle transponder unit to be reset to begin transmission over again. This permits an orderly response from the vehicle units to be obtained even though several units may be within the interrogation field at the same time and may be simultaneously attempting to transmit information to the interrogation station. Upon completion of transmission of an error free (verified) message from a transponder, the transponder is disabled from further transmission until the vehicle leaves the interrogation field.

Claims

1. A signalling system for identifying and monitoring a transponder unit including in combination:

a transponder unit including means normally in an initial condition for transmitting a unique signal train upon receipt of a transmitted interrogation signal;

an interrogation unit including means for generating and transmitting said interrogation signal and for receiving said unique signal train;

means in the interrogation unit responsive to reception of said unique signal train for terminating transmission of said interrogation signal and for initiating transmission of a verification signal train corresponding to the received signal train;

means in the transponder unit for comparing the verification signal train with the transmitted unique signal train and producing an output upon failure of verification;

means in the transponder unit for terminating transmission from and for resetting the means for transmitting the unique signal train in the transponder unit to the initial condition in response to said output from the comparing means; and

means in the interrogation unit for causing the interrogation unit to revert to transmission of the interrogation signal upon termination of transmission by the transponder unit.

2. The combination according to claim 1 wherein the verification signal train is transmitted simultaneously from the interrogation unit with transmission of the unique signal train from the transponder unit.

3. The combination according to claim 1 further including means responsive to the received verification signal train for controlling the operation of the means for transmitting the unique signal train from the transponder unit.

4. The combination according to claim 1 further including utilization circuit means and means in the interrogation unit for decoding the unique signal train transmitted thereto from the transponder unit and for supplying the decoded signal to utilization circuit means;

and wherein the unique signal train is composed of signals of a plurality of types and the verification signal train is transmitted to the transponder simultaneously with receipt of the unique signal train from the transponder, the verification signal sequence being in the form of a pulse sequence of a different predetermined relationship for verification of received signals of each of said types.

5. The combination according to claim 4 wherein two types of signals are transmitted by the transponder unit, both types being in the form of pulses of a predetermined type, the time of transmission of said pulses with respect to the verification signal train being transmitted by the interrogation unit determining which of the two types of signals is being transmitted by the transponder unit.

6. The combination according to claim 5 wherein the verification signal sequences are in the form of mark and space pulse sequences, and further including a shift register means for supplying the unique signal train from the transponder, the shift register supplying signals of first and second tyPes and wherein a signal of said one of said two types transmitted by the transponder unit is generated in response to a first type of signal supplied by the shift register simultaneously with a received space signal in the verification signal train and wherein transmission of a signal of said other of said two types from the transponder unit is generated in response to a second type of signal supplied by the shift register simultaneously with the receipt of a mark signal in the verification signal train from the interrogator unit.

7. The combination according to claim 6 further including means responsive to mark-to-space transitions in the received verification signal train for providing a sequence of shift pulses to the shift register to shift the same.

8. The combination according to claim 4 wherein the unique signal train comprises a message having a predetermined number of bits of information and the utilization circuit means includes a plurality of buffer storage register means each having a capacity for storing at least one message with means for supplying the message at an input bit rate to the register means for storage therein and further including output utilization means operable at an output bit rate different from the input bit rate at which the message is supplied to the register means, with means responsive to the storage of the message in a register means for enabling the output utilization means to remove the message from the register at said output bit rate.

9. The combination according to claim 8 wherein the plurality of register means includes at least two register means and further including means responsive to the filling of one of said register means for preventing the application of further information bits thereto and for transferring the application of information bits to the other of the register means first comparison means for sensing when all of said plurality of registers have been filled with messages for preventing the application of further information bits to the register means, and second comparison means for sensing when all of the registers are emptied for preventing the output utilization means from removing further information from said registers.

10. The combination according to claim 9 further including means for sequentially enabling the shift register means, wherein each register means has a capacity equal to the number of bits in each message, with first shift pulses for the shift register means being supplied to the shift registers at the input signal rate for storing data in the enabled shift register, with means for preventing the application of said first shift pulses to a register means upon the filling of the register means and for transferring control of the shift register means to the output utilization means, the output utilization means applying second shift pulses to the register at said output bit rate.

11. A signalling system for identifying and monitoring a transponder unit with an interrogation station transmitting interrogation and verification signals, the system including in combination:

transmission means in said transponder unit operable upon receipt of a transmitted interrogation signal for generating and transmitting a unique signal from said transponder unit;

means in the interrogation station responsive to the signals received by the interrogation station from the transponder unit for generating a sequence of verification signals for verifying said received signals;

means in the transponder unit for comparing received verification signals with the transmitted unique signal for producing an output upon failure of verification; and

means for terminating transmission from the transponder unit and for resetting the transmission means of the transponder unit to an initial condition in response to said output of the comparing means, causing the transponder unit to be rendered responsive to a transmitted interrogation signal for reinitiating transmission therefrom.

12. The coMbination according to claim 11 wherein the transponder unit transmits signals of first and second binary conditions and the verification signal sequence supplied by the interrogation station includes signal intervals of a first predetermined pattern for verifying said first binary condition and signal intervals of a second predetermined pattern for verifying said second binary condition, the transponder further including first clock circuit means enabled for operation during one of the signal intervals of each of the received verification patterns, the comparing means including gate circuit means responsive to the received verification signal, the transponder signal, and the output of the first clock circuit means for producing said output upon failure of verification.

13. The combination according to claim 12 wherein the first and second binary conditions are binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' and binary '"'"''"'"''"'"''"'"'0, '"'"''"'"''"'"''"'"' respectively and the signal format of the verification signal is such that the verification pattern for a binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' received from the transponder unit is in the form of a mark pulse of a first predetermined length followed by a space pulse of a first predetermined length and wherein the verification pattern for a binary '"'"''"'"''"'"''"'"'0'"'"''"'"''"'"''"'"' received from the transponder unit is in the form of a mark pulse of a second predetermined length followed by a space pulse of a second predetermined length, the length of at least one of the mark or space pulses used for verifying a binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' being different from the length of the corresponding mark or space pulses in the verification pattern for a binary '"'"''"'"''"'"''"'"'0,'"'"''"'"''"'"''"'"' with the gate circuit means including first and second verifier gates, the first gate being enabled by a binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' from the transponder and the second gate being enabled by a binary '"'"''"'"''"'"''"'"'0'"'"''"'"''"'"''"'"' from the transponder, with pulses from the first clock means being applied successively to the first and second verifier gates to produce outputs therefrom coinciding with the expected mark-to-space transitions in the verification patterns, and means responsive to the verification signal and the outputs of the first and second verifier gates for producing said output upon failure of the mark-to-space transitions of the verification signal to occur during the time an output is present from the first or second verifier gate.

14. The combination according to claim 12 further including a multi-stage shift register in the transponder with further gate circuit means interconnecting the output and input of the shift register to cause the register to be operated as a maximum sequence counter;

means responsive to the interrogation signals for supplying shift pulses to the shift register;

means responsive to a first predetermined code pattern stored in the shift register for enabling the transmission initiating means and for disabling the further gate means, permitting operation of the register as a shift register means responsive to operation of the transmission initiating means for storing a predetermined code pattern in the shift register corresponding to the sequence of first and second binary conditions to be transmitted from said transponder, the output of the final stage of the shift register providing the transponder output, and means responsive to pulse transitions in the received verification signal patterns for providing shift pulses for the shift register.

15. A transponder for use in a signalling system including an interrogation station transmitting a sequence of interrogation signals, the transponder including in combination:

a multistage shift register means, having at least an input stage and an output stage, each stage of the shift register means capable of being set to either first or second states of operation corresponding to two binary conditions and the stages storing an initial sequence of binary conditions upon initial energization;

means responsive to the interrogation signals for proViding a sequence of shift pulses to the shift register to shift the same;

means coupled with the input stage of the shift register for causing the shift register to be filled with a first predetermined pattern of binary conditions in response to the application of shift pulses thereto;

means coupled with the shift register for sensing the storage of said first predetermined pattern therein to produce a control signal;

means responsive to the control signal for supplying a second predetermined binary sequence for storage in the shift register; and

gate means responsive to the control signal and the output of the output stage of the shift register for providing an output signal train from the transponder.

16. The combination according to claim 15 wherein the first predetermined pattern is all stages of the shift register set to said first state of operation.

17. The combination according to claim 15 whereby the initial binary sequence established in the shift register upon initial energization is a random sequence and the means for causing the shift register to be filled with a first predetermined pattern of binary conditions includes second gate means responsive to the output of the output stage of the shift register for causing the register to be operated as a maximum sequence counter, the second gate means being disabled in response to said control signal.

18. The combination according to claim 15 further including means for transmitting said output signal train from the transponder and wherein the interrogation station further transmits a sequence of signals uniquely verifying signals received by the interrogation station from the transponder, the transponder further including means responsive to the receipt of the verification signals for providing shift pulses to the shift register.

19. A buffer storage circuit for temporarily storing messages in the form of a binary bit train of a predetermined length supplied to the buffer storage circuit at one bit rate and removed from the buffer storage circuit at a second bit rate including in combination:

a plurality of storage register means each having a capacity for storing at least one of said messages;

input control means for sequentially enabling the storage registers for the receipt of an input message;

input load means responsive to enabling of a register by the input control means to cause the storage of information therein at the bit rate of an input message;

first means coupled with the storage register means and responsive to the storage to capacity of a storage register means for causing the input control means to enable the next register in the sequence for the receipt of an input message;

register unload control means; and

second means coupled with the storage register means and responsive to the storage to capacity of a register for enabling the register unload control means to remove the message from the register at said second bit rate.

20. The combination according to claim 19 further including inhibiting means responsive to the storage to capacity of all of said plurality of registers for inhibiting operation of the input load means.

21. The combination according to claim 20 wherein the second means further senses completion of removal of a message from a register by the unload control means to enable the unload control means to remove a message from the next filled register in the sequence.

22. The combination according to claim 21 wherein the input control means includes a first counter means having a predetermined number of outputs corresponding to the number of register means and the second means includes a second counter means having a predetermined number of outputs corresponding to the number of register means and advanced to enable removal of messages sequentially from the register means, and wherein the inhibiting means includes first gating means responsive to corresponding outputs from the first and second counter means indicativE that information has not been removed from the register to which the first counting means has progressed for inhibiting operation of the input load means and further includes second gating means responsive to a combination of outputs of the first and second counter means, with the output of the second counter means corresponding to the register just prior to the one in the sequence which is enabled by an output from the first counter means, for inhibiting operation of the register unload control means.

23. A dual mode register circuit including in combination:

a multistage shift register means having at least an input stage and an output stage, each stage of the shift register means capable of being set to either first or second states corresponding to two binary conditions, and the stages storing information in the form of an initial sequence of binary conditions upon initial energization thereof;

means for providing a sequence of shift pulses to the register means to shift said information from the input stage to the output stage;

first gate means responsive to the output of the output stage of the register means for supplying input signals to the input stage of the register means to cause the register means to be operated as a maximum sequence counter;

means responsive to the storage of a predetermined information pattern in the register means for producing a control signal;

means responsive to the control signal for supplying a predetermined binary sequence for storage in the register means;

means responsive to the control signal for disabling operation of the gate means to cause a predetermined binary condition to be applied to the input stage of the register means; and

second gate means responsive to the control signal and the output of the output stage of the register means for providing an output signal train from the register means.

24. The combination according to claim 23 wherein the first gate means coupled with the output stage of the register means has at least first and second inputs, with the first input thereof being connected the output of the output stage of the register means;

and wherein the means for producing the control signal is a bistable multivibrator having first and second states of operation, and being set to a first state of operation supplying an enabling signal to the second input of the first gate means, with the output of the first gate means being coupled with the input of the input stage of the shift register and operating in response to the output of the output stage of the shift register to cause the shift register to be operated as a maximum sequence counter, the combination further including means coupled with the register means and responsive to the storage of the predetermined information pattern for causing the bistable multivibrator to change states of operation, thereby disabling the first gate means, causing a predetermined input to be supplied to the input stage of the register means so that further application of shift pulses thereto causes the register means to operate as a shift register.

25. A signalling system for identifying and monitoring a transponder unit with an interrogation station transmitting interrogation and verification signals, the system including in combination:

a multi-stage register means in the transponder and having at least an input stage and an output stage, each stage of the shift register means capable of being set to either first or second stages of operation corresponding to two binary conditions and the stages storing an initial random sequence of binary conditions upon initial energization thereof;

means responsive to the interrogation signals for providing a sequence of shift pulses to the shift register to shift information stored therein from the input stage to the output stage;

first gate means responsive to the output of the output stage of the shift register means for supplying signals to the input stage thereof to cause the regisTer means to operate as a maximum sequence counter;

means responsive to the storage of a maximum sequence count in the shift register for producing a control signal;

means responsive to the control signal for disabling the gate means, to enable the register means to be operated as a shift register;

transponder signal input means responsive to the control signal for supplying a predetermined unique binary sequence for storage in the shift register means;

transmission means in the transponder unit responsive to the control signal and the output of the output stage of the register means for providing an output signal train from the transponder;

means in the interrogation station responsive to the signals received by the interrogation station from the transponder unit for generating a sequence of verification signals verifying said received signals;

means responsive to the verification signals for providing a sequence of shift pulses to the shift register to shift the same;

means in the transponder unit for comparing the received verification signals with the transmitted unique binary sequence for producing an output upon failure of verification; and

means for terminating transmission from the transponder unit and for enabling the first gate means to cause the register means once again to be operated as a maximum sequence counter, the initial count stored therein corresponding to the states of the shift register stages at the time transmission is terminated, said means for terminating transmission further causing the control signal to be terminated and the transponder unit to be rendered responsive to transmitted interrogation signals for providing said sequence of shift pulses to the shift register.