PROGRAMMABLE COMPUTER-PERIPHERAL INTERFACE

• US 3,673,576 A
• Filed: 07/13/1970
• Issued: 06/27/1972
• Est. Priority Date: 07/13/1970
• Status: Expired due to Term

• Current Assignee: John C. Donaldson Jr
• Original Assignee: John C. Donaldson Jr
• Inventors: Donaldson, John C. Jr.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chirlin, Sydney R.
• Application Number:
  US05/054,556
• Time in Patent Office: 715 Days
• Field of Search: 340/172.5
• US Class Current: 710/20
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/32 using combination of interrupt and burst mode transfer

Abstract

An interfacing network for providing asynchronous data transfers directly with a computer memory and external devices. Computer instructions from the computer arithmetic unit are decoded in an executive control unit. Certain instructions ready an input or output channel control unit which thereafter controls data transfers with a selected external device. Each transfer is made directly with the computer memory and does not require interruption of the program being processed in the arithmetic unit. Once the input or output channel control unit assumes control of the transfer, the executive control unit is immediately available to perform other functions independently and concurrently. It may ready the other channel control unit and monitor external device and interface conditions including the readiness of an external device to transmit data. Certain monitored conditions cause the interfacing network to interrupt normal computer operation. Various control signals in the executive control unit are translated to and from control signals in the computer and external devices to permit the utilization of common instructions.

Claims

1. An interface for coupling a computer and a plurality of peripherals, the computer and peripherals each being adapted for transmitting and receiving data and control signals, the interface supervising data interchange between the computer and each peripheral and comprising:

A. control signal interchanging means adapted to be connected to the computer for interchanging data with the computer responsive to control signals from the computer and related interface control signals from and to the interface, B. a plurality of register means, each register means being adapted to have at least one peripheral connected thereto and being adapted for i. interchanging data and peripheral control signals with their respective peripherals ii. interchanging related control signals with the interface, and iii. interchanging data with the computer, C. control means connected to the control signal interchanging means and responsive to interface control signals from one of the register means or the control signal interchanging means to transmit control signals to the other of the means, and D. plural independent parallel data transfer means in parallel with the control signal interchanging means for coupling the computer and register means to transfer data therebetween, the control means independently controlling the register means and control signal interchanging means to thereby supervise data transfers between the computer and each peripheral.

2. An interface as recited in claim 1 wherein A. the control signal interchanging means transmits interface control signals in response to computer-issued instructions received by it, and B. the control means additionally comprises a register means selection decoder responsive to certain instruction words for identifying a selected peripheral by coupling one data transfer means to the register means associated with the selected peripheral.

3. An interface as recited in claim 2 wherein one peripheral transmits data from internally identified locations, the interface being adapted to respond to a computer issued initialization instruction identifying the peripheral and the internally identified storage location and including:

A. a counter in the associated register means for storing the address, and B. means responsive to the register means selection decoder for enabling the counter to store the identification.

4. An interface as recited in claim 2 additionally including means for sensing the conditions related to interface operations, the control means additionally comprising A. means responsive to a computer-issued monitoring instruction for identifying a specific sensing means for encoding a digital word indicating the state of the identified condition sensing means, and B. means for transferring the encoded word to the computer through the control signal interchanging means.

5. An interface as recited in claim 2 wherein one peripheral is adapted to receive data from the computer in response to a computer-issued output instruction, the register means selection decoder identifying the register means associated with one peripheral, the interface control means additionally comprising an output controller A. being responsive to the register means selection decoder and signal interchanging means for connecting a first data transfer means between the identified register means and the computer, and B. including means responsive to the control signal interchanging means and the register means for supervising the transfer of data from the computer to the selected peripheral through the register means.

6. An interface as recited in claim 5 wherein data is transferred from the computer as a plurality of data words, each data word containing a plurality of digital bits, the computer being programmed to issue, in succession, the output instruction word and an output word count identifying the number of data words to be transferred, the output controller additionally comprising A. an output counter for storing the output word count, B. means responsive to the application of the output instruction to the decoder and the control means to enable the output counter to store the output word count, C. means connected to the output counter for generating an output word count signal when the identified number of data words is transferred, and D. means responsive to the word count signal for disconnecting the first data transfer means for the register means.

7. An interface as recited in claim 6 wherein the computer has allotted successive memory locations for storing the data words and the computer is programmed to issue an initial output computer address in succession after the oUtput word count, A. the first data transfer means including i. an output computer address counter for storing the initial output computer address, ii. means responsive to the register selection decoder and the control means for enabling the output computer address counter to receive the initial output computer address, iii. means responsive to each transfer of data from the computer for altering the count in the output computer address counter, and iv. means connected to the output computer address counter for generating an output address signal indicating that data has been transferred from all allotted computer memory locations, and B. the output controller including means responsive to the output address signal for disconnecting the first data transfer means from the register means.

8. An interface as recited in claim 7 wherein the data is to be transferred to a specific peripheral location and wherein the computer is programmed to issue an output peripheral identifying the location in succession after the output computer address, the register means additionally comprising A. an output peripheral address counter for storing the output peripheral address, B. means responsive to the register selection decoder and the control means for enabling the output peripheral address counter to receive the instruction, and C. means responsive to the transfer of data from the register means for altering the location stored in the output peripheral address counter.

9. An interface as recited in claim 2 wherein one peripheral is adapted to transmit data to the computer in response to a computer-issued input instruction, the register selection decoder identifying the register means associated with the one peripheral, the interface control means additionally comprising an input controller A. being responsive to the register selection decoder and the control means for connecting second data transfer means between the identified register means and the computer, and B. including means responsive to the control signal interchange means and the register means for supervising the transfer of data to the computer from the selected peripheral through the register means.

10. An interface as recited in claim 9 wherein data is transferred to the computer as a plurality of data words, each data word containing a plurality of digital bits, the computer being programmed to issue, in succession, the input instruction and an input word count identifying the number of data words to be transferred, the input controller additionally comprising A. an input counter for storing the input word count, B. means responsive to the application of the input instruction to the operations decoder means and the control means to enable the input word counter to store the input word count, C. means connected to the input counter for generating an input word count signal when the identified number of data words is transferred, and D. means responsive to the input word count signal for disconnecting the second data transfer means from the register means.

11. An interface as recited in claim 10 wherein the computer has allotted successive memory locations for storing the data words and the computer is programmed to issue an initial input computer address in succession after the input word count, A. the second data transfer means including i. an input computer address counter for storing the initial input computer address, ii. means responsive to the register selection decoder and the control means for enabling the input computer address counter to receive the initial input computer address, iii. means responsive to each transfer of data to the computer for altering the count in the input computer address counter, and iv. means connected to the input computer address counter for generating an input address signal indicating that data has been transferred from all allotted computer Memory locations, and B. the input controller including means responsive to the input address signal for disconnecting the second data transfer means from the register means.

12. An interface as recited in claim 2 wherein one of the register means includes means responsive to a predetermined control portion of a computer issued control instruction identifying the register means and including:

A. means in the register means responsive to the control portion, and B. means responsive to the register means selection decoder and control signal interchanging means for enabling the control instruction responsive means to respond to the predetermined portion of the control instruction.

13. An interface as recited in claim 2 wherein one register means includes means responsive to a control word issued by the computer, the computer issuing an immediately preceding control initialization instruction identifying the register means and indicating that the control word immediately follows and including:

A. means in the associated register means responsive to the control word, and B. means responsive to the register means selection decoder and control signal interchanging means for enabling the control word responsive means to receive the control word when the control word is issued by the computer.

14. An interface as recited in claim 2 including a sensor for generating an interrupting signal in response to a predetermined condition, the control means additionally comprising:

A. a first signal generator for interrupting computer operation, B. a second signal generator for producing a signal identifying the predetermined condition to the computer, and C. means responsive to the first and second signal generators for transferring the second generated signal to the computer.

15. An interface as recited in claim 14 including a plurality of sensors for generating interrupting signals in response to a plurality of predetermined conditions, each condition being in a distinct condition class, A. the second signal generator including an encoder for encoding an instruction word for the computer identifying the class and the status of all conditions in the class, B. the control means includes means for transferring the encoded instruction word to the computer.

16. An interface as recited in claim 15 wherein sensors in one condition class are connected to each register means, each register means including means for storing the signals from a sensor and for generating information in response to conditions in peripherals connected to that register means, the storage means in each register means being connected in priority so signals from the storage means associated with a higher priority register means disable like signals from register means with a lower priority, each register means additionally including means for identifying the source of the signals.

17. An interface as recited in claim 15 wherein the certain of the sensors generate data interrupting signals when associated register means are prepared to transfer data to the computer, the interface being responsive to a computer issued masking instruction to control the response of the first and second signal generators to data interrupting signals and including:

A. signal masking means responsive to portions of the masking instruction and the data interrupting signals for enabling data interrupting signals defined by the masking instruction to energize the first and second signal generators, and B. means responsive to the control signal interchanging means for enabling the masking means to respond to the portions of the masking instruction.

18. An interface as recited in claim 2 additionally comprising A. an output control in a first data transfer means for controlling data transfers from the computer B. an input control in the second data transfer means for controlling data transfers to the computer, and C. meAns in the control means for readying the input and output controls in response to signals from the control signal interchanging means.

19. An interface as recited in claim 18 wherein the control signal interchanging means includes A. a first gate for transferring instructions from the computer to the control means, B. a second gate for transferring instructions from the control means to the computer, C. an interface decoder for generating interface control signals with each data and instruction transfer, and D. an interface encoder for generating computer control signals in response to interface control signals.

20. An interface as recited in claim 19 wherein the computer control signals include programmed operating instructions, the control means including A. an instruction register for storing computer issued operating instructions coupled through the first gate, B. an operations decoder for generating operation signals in response to predetermined portions of the operating instruction, C. a register selection decoder for generating signals in response to other portions of the operating instructions, and D. a timer responsive to the operations decoder and the interface decoder for enabling the instruction register to receive operating instructions.

21. An interface as recited in claim 20 including a plurality of sensors responsive to predetermined conditions in the interface and each peripheral and means responsive to certain condition sensors for generating interrupting signals, the conditions being categorized in a plurality of priority classes and the control means comprising A. an interrupting signal sensor connected to each condition sensor in a priority class for providing a signal identifying the priority class, B. priority gating means responsive to the interrupting signal sensors for recognizing the interrupting signal having the highest priority, and C. an interruption encoder responsive to the interrupting signal from the priority gating means and the signals from all condition sensors in the recognized class for generating an instruction identifying the category and the status of all interrupting signals in the category.

22. An interface as recited in claim 21 wherein one set of sensors and interrupting signal generator means in a first priority class monitor peripheral conditions for all peripherals connected to one register means, each register means being arranged in priority and including means for disabling the interrupting signal generator means in lower priority register means whereby peripheral condition information can be transferred to the computer from any register means in the interface.

23. An interface as recited in claim 21 wherein the interruption encoder is coupled to the input and output controls and the control means, the operations decoder being adapted to couple one condition sensing means to the interruption encoder.

24. An interface as recited in claim 23 wherein the peripheral includes internal control means responsive to predetermined digital bits in certain computer instructions and wherein the register means connected to the peripheral includes means connected to the operations decoder, the register selection decoder and the first gate for transferring the predetermined digital bits to the peripheral internal control means.

25. An interface as recited in claim 23 wherein at least one peripheral is adapted to transfer data to the computer and the register means connected thereto includes A. an input data register for transferring data from the peripheral to the computer B. means for generating an input data ready signal for the input control and one interrupting signal sensor when the input data register is loaded and C. at least one condition sensor responsive to internal peripheral conditions, the internal peripheral condition sensor being connected to the interrupting signal sensor.

26. An interface as reciteD in claim 25 wherein the control means includes A. a mask generator responsive to certain instructions from the computer and the operations decoder for generating masking signals, B. means in the one interrupting signal sensor responsive to coincidence of data ready signals and masking signals for controlling the response of the one interrupting signal sensor.

27. An interface as recited in claim 25 adapted to transfer data directly to a specific computer memory location wherein the input control includes A. an input computer address generator for identifying the computer memory location, B. an input register means selector responsive to the register selection decoder for enabling one register means C. an input controller connected to the control signal interchanging means and the control means for initiating a data transfer from the input data register to the computer when the input data register is ready to transmit data.

28. An interface as recited in claim 27 wherein data is to be transferred from the peripheral as a plurality of digital words for storage in a plurality of allotted successive computer memory locations, the computer being adapted to issue, in succession, an input instruction, an input word count instruction identifying the number of data words to be transferred and an input computer memory address instruction identifying the initial computer memory location, the input controller including A. an input word counter for storing the input word count instruction, B. means responsive to the application of the input instruction to the operations decoder to enable the input word counter to store the input word count instruction, C. means connected to the register means and the input word counter for altering the count therein with each transfer of data from the input data register, the input controller including a condition sensor for generating an interrupting signal when all data words have been transferred, D. an input computer address counter for storing the input computer address instruction, E. means responsive to the application of the input instruction word to the operations decoder to enable the input computer address counter to store the input computer address instruction, and F. means connected to the interface decoder and the input computer address counter for altering the count therein with each transfer of data to the computer memory, the input controller including another condition sensor for generating an interrupting signal when all allotted computer memory locations have been utilized.

29. An interface as recited in claim 28 wherein at least one peripheral transmits data from successive, internally identified locations, the computer being adapted to issue, in succession, an initialization instruction and an input peripheral address instruction identifying the initial location, the register means including A. an input peripheral address counter for storing the input peripheral address instruction, and B. means connected to the operations decoder and the register selection decoder for enabling the input peripheral address counter to store the input peripheral address instruction, the counter being altered with the transfer of data from each internal location in the peripheral.

30. An interface as recited in claim 27 wherein certain conditions indicate a loss of data being transferred to the computer, the input controller including at least one condition sensor for sensing the data loss conditions and a second interrupting signal sensor for responding to the data loss signal for signalling the priority gating means and interruption encoder to interrupt computer operation.

31. An interface as recited in claim 28 wherein data is transferred to the computer as computer data words of a given number of discrete digital bits in parallel, wherein data is transferred from the input data register as an interface data word of another number oF discrete digital bits in parallel, at least one computer data word being stored in the input data register and wherein the input instruction identifies the number of computer data words in an interface data word, the input data transfer means additionally including A. a second register for receiving all data bits from the input data register in a single transfer as in interface data word, B. a transfer decoder responsive to the portion of the instruction identifying the number of computer data words in each interface data word, and C. routing means connected to the transfer decoder and the second register for transferring the given number of parallel bits to the computer from successive portions of the second register.

32. An interface as recited in claim 28 adapted to be responsive to monitoring instructions from the computer, the interface additionally comprising A. a bus connected to the interruption encoder for transmitting monitoring information thereto for transfer to the computer, B. means for transferring the count in the input word counter onto the bus in response to one monitoring instruction, C. means for transferring the signals in the input register means selector onto the bus in response to another monitoring instruction, D. means for transferring the count in the input computer address counter onto the bus in response to another monitoring instruction.

33. An interface as recited in claim 23 wherein at least one peripheral is adapted to transfer data from the computer and the register means connected thereto includes A. an output data register for transferring data from the computer to the peripheral, B. means for generating an output data ready signal for the output control when the output data register has been loaded into the peripheral, C. at least one condition sensor responsive to internal peripheral conditions, the internal peripheral condition sensor being connected to the interrupting signal sensor.

34. An interface as recited in claim 33 adapted to transfer data directly from a specific computer memory location wherein the output control includes A. an output computer address generator for identifying the computer memory location, B. an output register means selector responsive to the register selection decoder for enabling one register means, C. an output controller connected to the control signal interchanging means and the control means for initiating a data transfer to the output data register means from the computer when the output data register is ready to accept data.

35. An interface as recited in claim 34 wherein data is to be transferred to the peripheral as a plurality of digital words from storage in a plurality of allotted successive computer memory locations, the computer being adapted to issue, in succession, an output instruction, an output word count instruction identifying the number of data words to be transferred and an output computer memory address instruction identifying the initial computer memory location, the output controller including i. an output word counter for storing the output word count instruction, ii. means responsive to the application of the output instruction to the operations decoder to enable the output word counter to store the output word count instruction, iii. means connected to the register means and the output word counter for altering the count therein with each transfer of data to the output data register, the output controller including a condition sensor for generating an interrupting signal when all data words have been transferred, iv. an output computer address counter for storing the output computer address instruction, v. means responsive to the application of the output instruction word to the operations decoder to enable the output computer address counter to store the output computer address instruction, and vi. means connected to the interface decOder and output computer address counter for altering the count therein with each transfer of data from the computer memory, the output controller including another condition sensor for generating an interrupting signal when all allotted computer memory locations have been utilized.

36. An interface as recited in claim 35 wherein at least one peripheral accepts data in successive, internally identified locations, the computer being adapted to issue an output peripheral address instruction in succession after the output computer address instruction, the register means including A. an output peripheral address counter for storing the output peripheral address instruction, and B. means connected to the operations decoder and the register selection decoder for enabling the output peripheral address counter to store the output peripheral address instruction, the counter being altered with the transfer of data to each internal location in the peripheral.

37. An interface as recited in claim 35 wherein certain conditions indicate loss of data being transferred from the computer, the output controller including at least one condition sensor for sensing the data loss conditions and a second interrupting signal sensor for responding to the data loss signal for signalling the priority gating means and interruption encoder to interrupt computer operation.

38. An interface as recited in claim 35 wherein data is transferred from the computer as computer data words of a given number of discrete digital bits in parallel, wherein data is transferred to the output data register as an interface data word of another number of discrete digital bits in parallel, at least one computer data word being stored in the output data register and wherein the output instruction identifies the number of computer data words in an interface data word, the output data transfer means additionally including A. a second register for transferring all data bits to the output data register in a single transfer as an interface data word, B. a transfer decoder responsive to the portion of the instruction identifying the number of computer data words in each interface data word, and C. routing means connected to the transfer decoder and the second register for transferring the given number of parallel bits from the computer to successive portions of the second register.

39. An interface as recited in claim 35 adapted to be responsive to monitoring instructions from the computer, the interface additionally comprising A. a bus connected to the interruption encoder for transmitting monitoring information thereto for transfer to the computer, B. means for transferring the count in the output word counter onto the bus in response to one monitoring instruction, C. means for transferring the signals in the output register means selector onto the bus in response to another monitoring instruction, D. means for transferring the count in the output computer address counter onto the bus in response to another monitoring instruction.