METHOD FOR MEASURING RESISTIVITY

• US 3,676,775 A
• Filed: 05/07/1971
• Issued: 07/11/1972
• Est. Priority Date: 05/07/1971
• Status: Expired due to Term

• Current Assignee: Andrew Dupnock, Edward F. Gorey, William A. Keenan
• Original Assignee: Andrew Dupnock, Edward F. Gorey, William A. Keenan
• Inventors: Gorey, Edward F., Keenan, William A., Dupnock, Andrew
• Primary Examiner(s): Krawczewicz, Stanley T.
• Application Number:
  US05/141,307
• Time in Patent Office: 431 Days
• Field of Search: 324/64,158R,158D,158P
• US Class Current: 324/717
• CPC Class Codes: G01N 27/041 of a solid body
• CPC Class Codes: G01R 31/2637 for testing other individual devices G01R31/2608 - G01R31/2632, G01R31/27 take precedence

Abstract

The method for measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus wherein the base has at least two high conductivity diffused regions, positioning two current probes directly over two separate diffused regions in contact with the surface of the epitaxial layer, placing two spaced voltage probes in contact with the epitaxial layer in a generally intermediate position relative to the current probes, inducing a current through the current probes and measuring the voltage drop between the voltage probes, calculating the bulk resistivity in accordance with the expression:

Claims

1. A method of measuring the bulk resistivity of an epitaxial semiconductor layer on a monocrystalline semiconductor base with a 4-point probe apparatus comprising, forming at least two-spaced high conductivity diffused regions in the base, depositing an epitaxial layer of semiconductor material on the base, positioning two current probes directly over said diffused regions in contact with the surface of said epitaxial layer, placing two-spaced voltage probes in contact with the surface of said epitaxial layer in generally intermediate positions relative said current probes, introducing through said current probes an electrical current flow through the epitaxial layer between the probes, measuring the voltage drop in the epitaxial layer across said voltage probes, calculating the bulk resistivity in accordance with the expression:

Resistivity V/I X C.F. X t, where V is the voltage drop, I is the current flow, t is the epitaxial layer thickness, and dC.F. is an empirical correction factor that is a function of the voltage probe spacing and the percent area of the substrate covered by the diffused regions.

2. The method of claim 1 wherein said voltage probes are placed over two separate sub-surface high conductivity diffused regions in said base.

3. The method of claim 2 wherein said base and overlying semiconductor layer includes a plurality of subsurface high conductivity diffused regions intermediate said diffused regions beneath the current and voltage probes.

4. The method of claim 3 wherein said diffused regions under said voltage and current probes are tests sites on a wafer at an intermediate stage in the fabRication of integrated circuit devices.

5. The method of claim 1 wherein said thickness of the epitaxial layer is in the range of 0.2 to 15 microns.

6. The method of claim 1 wherein said semiconductor material is silicon.