STABILIZED COMPLEMENTARY MICRO-POWER SQUARE WAVE OSCILLATOR

• US 3,676,801 A
• Filed: 10/28/1970
• Issued: 07/11/1972
• Est. Priority Date: 10/28/1970
• Status: Expired due to Term

• Current Assignee: Fuad H. Musa
• Original Assignee: Fuad H. Musa
• Inventors: Musa, Fuad H.
• Primary Examiner(s): Kominski, John
• Application Number:
  US05/084,602
• Time in Patent Office: 622 Days
• Field of Search: 331/116R 58/23
• US Class Current: 331/116.0FE
• CPC Class Codes: G04F 5/06 using piezoelectric resonators
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03K 3/3545 Stabilisation of output, e.g. using crystal

Abstract

A square wave oscillator is shown utilizing a P channel and an N channel Metal-Oxide-Silicon Field Effect Transistor (MOSFET) in combination with a quartz crystal for generating a frequency stabilized square wave signal suitable for use in a wristwatch.

Claims

1. An oscillator circuit of the type including complementary metal-oxide-semiconductor;

field-effect-transistors (MOSFET), comprising;

a source of potential having at least a first level of potential and a second level of potential, a first, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a second, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, said substrate electrode of each MOSFET being connected to said source electrode of said same MOSFET, an output terminal, said source electrode of said first MOSFET being connected to said first level, an output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said first and second MOSFETS being interconnected at a first junction with said first end of said output capacitor for providing a charging path for said output capacitor through said first MOSFET and for providing a discharging path for said output capacitor through said second MOSFET, said gate electrodes being interconnected and forming a second junction, an input capacitor being connected between said second junction and said second level for participating in the establishment of a bias potential for said drain electrodes, said source electrode of said second MOSFET being connected to said second level, a crystal for setting the frequency of oscillation is connected between said first and second junctions, and a starting resistor is connected between said first and second junctions for ensuring that the interconnected first and second MOSFETS are not initially latched in a static state.

2. An oscillator circuit as recited in claim 1, wherein:

said first MOSFET is a P channel MOSFET, said second MOSFET is an N channel MOSFET, and said second level of said potential source is lower than said first level.

3. An oscillator circuit as recited in claim 1, wherein:

said first MOSFET is an N channel MOSFET, said second MOSFET is a P channel MOSFET, and said second level of said potential source is greater than said first level.

4. An oscillator circuit as recited in claim 2, and further comprising:

a third P channel, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a fourth N channel, enhancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each said third and fourth MOSFETS being connected to said source electrode of said same MOSFET, a second output terminal, said source electrode of said third MOSFET being connected to said first level, a second output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end. said drain electrodes of said third and fourth MOSFETS being interconnected at a third junction with said first end of said second output capacitor for providing a charging path for said output capacitor through said third MOSFET and for providing a discharging path for said second output capacitor through said fourth MOSFET, said gate electrodes of that third and fourth MOSFETS being interconnected to said first junction, and said source electrode of said fourth MOSFET being connected to said second level whereby, output signals, complementary in fOrm, are available at said first output terminal and said second output terminal.

5. The oscillator as recited in claim 1, and further including:

a capacitor in series connection with said crystal for providing temperature frequency stabilization and frequency trimming.

6. The oscillator as recited in claim 1, and further including:

a capacitor in parallel connection with said crystal for providing frequency trimming.

7. The oscillator as recited in claim 5, and further including:

a capacitor in parallel connection with said crystal for providing frequency trimming.

8. An oscillator circuit as recited in claim 3, and further comprising:

a third N channel, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a fourth P channel, enhancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each of said third and fourth MOSFETS being connected to said source electrode of said same MOSFET, a second output terminal, said source electrode of said third MOSFET being connected to said first level, a second output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said third and fourth MOSFETS being interconnected at a third junction with said first end of said second output capacitor for providing a charging path for said output capacitor through said third MOSFET and for providing a discharging path for said second output capacitor through said fourth MOSFETS, said gate electrodes of that third and fourth MOSFETS being interconnected to said first junction, and said source electrode of said fourth MOSFET being connected to said second level whereby, output signals, complementary in form, are available at said first output terminal and said second output terminal.

9. An oscillator circuit of the type including complementary metal-oxide semiconductor;

field-effect-transistors (MOSFET), comprising;

a source of potential having at least a first level of potential and a second level of potential which is lower than said first level, a first, enhancement mode, P-channel MOSFET having source, drain, gate, and substrate electrodes, a second, enhancement mode, N-channel MOSFET having source, drain, gate, and substrate electrodes, said substrate electrode of each MOSFET being connected to said source electrode of said same MOSFET, an output terminal, said source electrode of said first MOSFET being connected to said first level, an output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said first and second MOSFETS being interconnected at a first junction with said first end of said output capacitor for providing a charging path for said output capacitor through said first MOSFET and for providing a discharging path for said output capacitor through said second MOSFET, said gate electrodes being interconnected and forming a second junction, an input capacitor being connected between said second junction and said second level for participating in the establishment of a bias potential for said drain electrodes, said source electrode of said second MOSFET being connected to said second level, a starting resistor is connected between said first and second junctions for ensuring that the interconnected first and second MOSFETS are not initially latched in a static state, a third P channel, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a fourth N channel, enhancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each said third and fourth MOSFETS being connected to said sourCe electrode of said same MOSFET, a second output terminal, said source electrode of said third MOSFET being connected to said first level, a second output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said third and fourth MOSFETS being interconnected at a third junction with said first end of said second output capacitor for providing a charging path for said output capacitor through said third MOSFET and for providing a discharging path for said second output capacitor through said fourth MOSFET, said gate electrodes of that third and fourth MOSFETS being interconnected to said first junction, and said source electrode of said fourth MOSFET being connected to said second level, a fifth P channel, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a sixth N channel, enchancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each of said third and fourth MOSFETS being connected to said source electrode of said same MOSFET, a third output terminal, said source electrode of said fifth MOSFET being connected to said first level, a third output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said fifth and sixth MOSFETS being interconnected at a fourth junction with said first end of said third output capacitor for providing a charging path for said output capacitor through said fifth MOSFET and for providing a discharging path for said third output capacitor through said sixth MOSFET, said gate electrodes of said fifth and sixth MOSFETS being interconnected to said third junction, said source electrode of said sixth MOSFET being connected to said second level, and a crystal being connected to said fourth junction whereby, output signals, complementary in form, are available at said second and third output terminals.

10. An oscillator circuit of the type including complementary metal-oxide-semiconductor;

field-effect-transistors (MOSFET), comprising;

a source of potential having at least a first level of potential and a second level of potential which is greater than said first level, a first, enhancement mode N-channel MOSFET having source, drain, gate, and substrate electrodes, a second, enhancement, P-channel MOSFET having source, drain, gate, and substrate electrodes, said substrate electrode of each MOSFET being connected to said source electrode of said same MOSFET, an output terminal, said source electrode of said first MOSFET being connected to said first level, an output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said first and second MOSFETS being interconnected at a first junction with said first end of said output capacitor for providing a charging path for said output capacitor through said first MOSFET and for providing a discharging path for said output capacitor through said second MOSFET, said gate electrodes being interconnected and forming a second junction, an input capacitor being connected between said second junction and said second level for participating in the establishment of a bias potential for said drain electrodes, said source electrode of said second MOSFET being connected to said second level, a starting resistor is connected between said first and second junctions for ensuring that the interconnected first and second MOSFETS are not initially latched in a static state, a third N channel, enchancement mode MOSFET having source, drain, gate, and substratE electrodes, a fourth P channel, enhancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each of said third and fourth MOSFETS being connected to said source electrode of said same MOSFET, a second output terminal, said source electrode of said third MOSFET being connected to said first level, a second output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said third and fourth MOSFETS being interconnected at a third junction with said first end of said second output capacitor for providing a charging path for said output capacitor through said third MOSFET and for providing a discharging path for said second output capacitor through said fourth MOSFET, said gate electrodes of that third and fourth MOSFETS being interconnected to said first junction, and said source electrode of said fourth MOSFET being connected to said second level, a fifth N channel, enhancement mode MOSFET having source, drain, gate, and substrate electrodes, a sixth P channel, enhancement mode MOSFET having source, drain, gate and substrate electrodes, said substrate electrodes of each of said fifth and sixth MOSFETS being connected to said source electrode of said same MOSFET, a third output terminal, said source electrode of said fifth MOSFET being connected to said first level, a third output capacitor participating in the establishment of a bias potential and having a first end and a second end and being connected to said second level by said second end, said drain electrodes of said fifth and sixth MOSFETS being interconnected at a fourth junction with said first end of said third output capacitor for providing a charging path for said output capacitor through said fifth MOSFET and for providing a discharging path for said third output capacitor through said sixth MOSFET, said gate electrodes of said fifth and sixth MOSFETS being interconnected to said third junction, said source electrode of said sixth MOSFET being connected to said second level, and a crystal being connected to said fourth junction whereby, output signals, complementary in form, are available at said second and third output terminals.