DIGITAL COMMUNICATION SYSTEM

• US 3,678,391 A
• Filed: 04/06/1970
• Issued: 07/18/1972
• Est. Priority Date: 04/06/1970
• Status: Expired due to Term

• Current Assignee: Warren G. Gough
• Original Assignee: Warren G. Gough
• Inventors: Gough, Warren G.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Leibowitz, Barry
• Application Number:
  US05/025,841
• Time in Patent Office: 834 Days
• Field of Search: 343/177 325/55,64,51,53 340/151,152 129/15
• US Class Current: 370/313
• CPC Class Codes: H04W 84/08 Trunked mobile radio systems

Abstract

The dispatcher'"'"''"'"'s equipment and each mobile unit in a police patrol car has a standard frequency modulated (FM) transceiver for communicating with voice messages. Each mobile unit also has digital circuitry for identifying itself, selecting a prescribed digital code message, synchronizing its operation with that of circuitry in the dispatcher'"'"''"'"'s equipment, converting the digital message to an audio signal for transmission by the FM transceiver, converting an audio signal received by the transceiver to a digital message, and presenting a visual display of digital messages transmitted and received. The dispatcher'"'"''"'"'s equipment includes similar circuitry for selecting, displaying, transmitting and receiving digital messages. In order to synchronize transmitting and receiving circuitry, each receiving circuit resets counters in an associated clock circuit on the leading edge of each digital input having a high logic level. Each mobile unit is manually actuated to transmit a signal acknowledging receipt of a digital message. The dispatcher'"'"''"'"'s equipment automatically transmits a signal acknowledging receipt of a digital message. Routine digital messages from mobile units such as requests to go off duty for lunch or for a status check on an automobile license plate number are processed automatically by a digital computer in the dispatcher'"'"''"'"'s equipment. The assignment/availability status of mobile units and recent digital messages received therefrom and transmitted thereto are visually displayed on the dispatcher'"'"''"'"'s equipment.

Claims

1. In a two-way communication system, a radio unit capable of transmitting and receiving both voice and digital electrical signals comprising a transceiver for transmitting and receiving electrical signals, antenna means coupling electrical signals to and from said transceiver, clock means for generating clock pulses having high and low pulse repetition frequencies, control means for selectively producing a digital signal characterized by binary amplitude levels comprising means for generating a digital synchronization word and a unique digital word identifying a particular radio unit, means for generating a digital message word, logic means for combining the digital words from said first and second generating means for assembling the selected digital signal, and message means selectively manually actuated to generate a control pulse for initiating transmission of the assembled digital signal, said logic means being responsive to said control pulse for selectively passing said low frequency clock pulses, means responsive to the output of said logic means for converting said selected digital signal to an aNalog signal comprising a first digital compiler responsive to the operation of said logic means for simultaneously receiving into prescribed stages thereof said digital identification, synchronization and message words and responsive to said clock pulses passed by said logic means for sequentially advancing the contents of said first compiler for producing a serial digital output signal, and an encoder responsive to the first serial digital signal for generating an electrical signal having one frequency when the amplitude of said serial signal has one binary value and generating another electrical signal having another frequency when the amplitude of said serial digital signal is a second binary value, said transceiver being responsive to said analog signals from said converting means for transmitting same through said antenna means and responsive to such signals from said antenna means for producing received analog signals, means connected to the output of said transceiver for automatically reconverting received analog signals to corresponding binary amplitude level received digital signals, and indicating means responsive to the outputs of said logic means and said reconverting means for providing readable indications of selected and received digital signals, respectively.

2. A radio unit according to claim 1 wherein said reconverting means comprises a decoder responsive to output signals from said transceiver for generating a second serial digital output signal corresponding to a received digital signal, the amplitude of said second serial digital signal having one binary value when the transceiver output signal has one frequency and having a second binary value when the transceiver output signal has another frequency, and a synchronization circuit responsive to the output signal from said decoder and to the high frequency clock pulses from said clock means for synchronizing same.

3. A radio unit according to claim 2 wherein said synchronization circuit includes means for resetting clock means on a transition of the nth serial digital signal where n is an integer greater than 1.

4. A radio unit according to claim 3, said clock means comprising an oscillator producing a train of pulses having a fixed frequency, and counting means having a plurality of stages and being responsive to pulses from said oscillator for producing said low frequency clock pulses having a frequency that is an integral multiple of the fixed frequency, said synchronization circuit being responsive to the nth serial digital signal and pulses in said counting means for resetting selected states thereof on a transition of the nth serial digital signal.

5. A radio unit according to claim 4 wherein the fixed frequency is greater than the frequency of said low frequency clock pulses and said first counting means comprises a plurality of divider circuits connected in series to the output of said first oscillator, said synchronization means being responsive to the output of one of said divider circuits for resetting another divider circuit producing an output signal having a frequency less than the output frequency of said one divider circuit on generation of a predetermined output pulse of said one divider circuit following a transition of the nth serial digital output signal.

6. A radio unit according to claim 2 wherein said reconverting means includes a pulse control circuit responsive to the output of said clock means for selectively passing said low frequency clock pulses, a second digital compiler responsive to said low frequency clock pulses from said control circuit for advancing said second serial digital signal through stages of said second compiler, and a decoding circuit responsive to the contents of predetermined stages of said second compiler for producing a second control pulse only when said predetermined stages thereof contain a particular digital identification cOde word unique to the radio unit, said control circuit also being responsive to the second control pulse for blocking the low frequency clock pulses for causing said second compiler to hold the contents in the stages thereof.

7. A radio unit according to claim 6 wherein said indicating means is responsive to contents of said second compiler for producing a visual display of received digital signals.

8. A radio unit according to claim 6 wherein said decoding circuit comprises first and second logic elements for producing outputs having prescribed values when the contents of particular different sets of stages of said second compiler contain a specified digital synchronization code word, a third logic element producing an output having a prescribed value when a particular set of stages of said second compiler contains a unique digital identification code associated only with this unit, and a fourth logic element responsive to the outputs of said first, second and third logic elements having the prescribed values for producing the second control pulse.

9. A radio unit according to claim 8 wherein said pulse control circuit comprises a fifth logic element having a first input receiving said low frequency clock pulses and having a second input responsive to the second control pulse from said decoder circuit.

10. A radio unit according to claim 2 including means for recirculating said first serial digital signal through said first compiler, said logic means being responsive to the low frequency clock pulses for blocking these pulses from said first compiler when the first serial digital signal has circulated a predetermined number of times therethrough.

11. A radio unit according to claim 2 wherein said logic means is responsive to said low frequency clock pulses for producing high frequency clock pulses having a frequency greater than and being a multiple of the frequency of the low frequency clock pulses, said encoder being responsive to said high frequency clock pulses for chopping at the frequency thereof the first serial digital signal having one binary value.

12. A radio unit according to claim 2 wherein said converting means comprises a second oscillator responsive to the first serial digital signal having an amplitude of one binary value for producing an electrical signal having one audio frequency, and a third oscillator responsive to the first serial digital signal having an amplitude of the other binary value for producing an electrical signal having a different audio frequency.

13. A radio unit according to claim 2 wherein said message word generating means comprises switch means for selectively specifying transmission of digital code message words and digital status check message words, first means for selecting one of several predetermined digital code message words, and second means for selecting a digital word representing a motor vehicle license plate number.

14. A radio unit according to claim 13 wherein said first selecting means comprises a first switch having a plurality of positions each corresponding to a different predetermined digital code.

15. A radio unit according to claim 14 wherein said second selecting means comprises a plurality of second switches, some of said second switches having positions designating alphabetic characters and other of said second switches having positions designating numeric characters.

16. A radio unit according to claim 15 wherein said indicating means comprises a plurality of tubes for displaying characters selected by said second switches.

17. A radio unit according to claim 16, comprising a third switch having a first position for electrically interchanging the selected characters that are displayed on particular tubes, and having a second position, said indicating means comprising a first light that is illuminated when said third switch is in the first position.

18. A radio unit according to claim 6 wherein said indicating means includes A second light electrically connected to said second compiler and adapted to be illuminated when a received digital communication is held in said compiler.

19. A radio unit according to claim 6 wherein said control means comprises third means for selecting for transmission a digital code word acknowledging receipt of a digital signal.

20. A radio unit according to claim 19 wherein said reconverting means includes reset switch means for causing the pulse control circuit to pass the low frequency clock pulses to said second compiler for advancing the contents thereof to enable it to receive a subsequently received digital signal.

21. A radio unit according to claim 2 wherein said decoder comprises a filter circuit connected to the output of said transceiver and passing only signals from said transceiver having the one frequency, a first detector connected to the output of said filter circuit and producing a signal having an amplitude proportional to the energy in signals passed by said filter circuit, and a second detector connected to the output of said first detector and producing a signal having a constant amplitude only when the amplitude of the signal from said first detector is greater than a prescribed threshold level.

22. A radio unit according to claim 12 wherein said decoder comprises a third frequency selective detector circuit producing an output signal having a first constant amplitude only when the frequency of signals passed by said transceiver is the one frequency, a fourth frequency selective detector circuit producing an output signal having a second constant amplitude only when the frequency of signals passed by said transceiver is the other frequency, and means for combining the output signals of said third and fourth detector circuits for producing the second serial digital signal.

23. A radio unit according to claim 2 wherein said first digital compiler comprises a first shift register having a plurality of stages including first and last stages, and a first buffer register responsive to the first control pulse for entering the assembled digital message into stages thereof, said first shift register being responsive to the low frequency clock pulses passed by said logic means for serially advancing the contents from said last stage for producing the first serial digital signal, and means for coupling the first serial digital signal from the output of said last stage to the input of said first stage for recirculating the contents of said plurality of stages.

24. A radio unit according to claim 2 wherein said reconverting means includes a digital converter responsive to the output of said decoder for detecting when a received digital signal is in said decoder output.

25. A radio unit according to claim 24 wherein said digital converter comprises means for dividing the second serial digital signal into a prescribed number of parts each having a predetermined length, and means for comparing corresponding parts of two successively received second serial digital signals for confirming that a received digital message is present.

26. A radio unit according to claim 25 wherein said second dividing means comprises a second shift register responsive to low frequency clock pulses for advancing signals from said decoder therethrough, means for detecting when a second serial digital signal is in said second shift register, and means for outputting from said second shift register said parts of second serial digital signals.

27. A radio unit according to claim 26 wherein said outputting means comprises storing means responsive to the operation of said detecting means for receiving the contents of selected stages of said second shift register, said comparing means receiving the contents of said storing means.

28. A radio unit according to claim 27 wherein said detecting means includes timing means producing a train of clock pulses and periodically producing tHird control pulses, said storing means comprising a third shift register responsive to said clock pulses for advancing the contents thereof.