NON-MAIN BEAM REFLECTED IFF INTERROGATION REJECTOR
First Claim
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1. In a transponder receiving IFF interrogation signals and emitting reply signals, a suppression network for suppressing reply signals for reflected interrogation signals comprising:
- means for determining the time interval between said reflected interrogation signal and a side lobe suppression signal comprising two pulses separated by a predetermined time interval;
storage means for storing said determined time interval; and
means for suppressing ensuing transponder reply signals time separated from a sidelobe suppression signal by said stored time interval.
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Abstract
A technique of utilizing the measured time between reception of a sidelobe suppression signal and reflected signals of an IFF interrogation to inhibit further responses to succeeding reflected path interrogations.
9 Citations
7 Claims
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1. In a transponder receiving IFF interrogation signals and emitting reply signals, a suppression network for suppressing reply signals for reflected interrogation signals comprising:
- means for determining the time interval between said reflected interrogation signal and a side lobe suppression signal comprising two pulses separated by a predetermined time interval;
storage means for storing said determined time interval; and
means for suppressing ensuing transponder reply signals time separated from a sidelobe suppression signal by said stored time interval.
- means for determining the time interval between said reflected interrogation signal and a side lobe suppression signal comprising two pulses separated by a predetermined time interval;
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2. A suppression network as recited in claim 1, wherein said determining means comprises a shift register, a first and second coincidence means, a counter, a free running pulse generator and a switch, wherein said sidelobe suppression signal sets said shift register to produce an output from said first coincidence means whereby said switch produces a continuous output to one input of said second coincidence means, the other input of said second coincidence means being supplied by said pulse generator, the output signal of said second coincidence means initiating said counter, said reply signal transferring the count in said counter at that instant into said storage means.
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3. A suppression network as recited in claim 2 including a third coincidence means connected between said counter and switch for resetting said switch upon said counter reaching a predetermined count.
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4. A suppression network as recited in claim 3 wherein said suppressing means comprises:
- means for delaying said reply signal; and
fourth coincidence means for receiving said delayed reply signal and an indicating means signal, said fourth coincidence means passing a signal if said indicating means indicates no two counts stored in said storage means are identical.
- means for delaying said reply signal; and
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5. A suppression network as recited in claim 4 wherein said indicating means comprises:
- delay means for delaying a first count signal a predetermined time;
fifth coincidence means for receiving said delayed count signal and an ensuing identical count signal, said fifth coincidence means output signal suppressing said fourth coincidence means.
- delay means for delaying a first count signal a predetermined time;
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6. In a transponder receiving IFF interrogation signals and emitting reply signals, the network comprising:
- indicating means for indicating the nonpresence of a sidelobe suppression signal comprising two pulses separated by a predetermined time interval;
first coincidence means connected to said indicating means and said transponder receiver for triggering said transponder transmitter upon receiving a reply signal and said indicating signal.
- indicating means for indicating the nonpresence of a sidelobe suppression signal comprising two pulses separated by a predetermined time interval;
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7. The network of claim 6, wherein said indicating means comprises:
- a shift register, second coincidence means connected to said shift register for indicating the presence of said sidelobe suppression signal in said shift register; and
an inverter connected between said first and second coincidence means.
- a shift register, second coincidence means connected to said shift register for indicating the presence of said sidelobe suppression signal in said shift register; and
Specification