LOW LEVEL DC AMPLIFIER WITH AUTOMATIC ZERO OFFSET ADJUSTMENT

• US 3,681,703 A
• Filed: 11/16/1970
• Issued: 08/01/1972
• Est. Priority Date: 11/16/1970
• Status: Expired due to Term

• Current Assignee: David August Johnson
• Original Assignee: David August Johnson
• Inventors: Johnson, David August
• Primary Examiner(s): Lake, Roy
• Assistant Examiner(s): Mullins, James B.
• Application Number:
  US05/089,668
• Time in Patent Office: 624 Days
• Field of Search: 330/9,11,3R,3D,69,51,149
• US Class Current: 330/9
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection

Abstract

A low level dc amplifier which amplifies low level signals and automatically adjusts the output signal thereof to eliminate the output offset voltage.

Claims

1. In combination, first amplifier means having at least one input terminal for receiving an input signal and an output terminal, second amplifier means comprising a sample and hold amplifier having at least one input terminal for receiving an input signal and an output terminal, differential amplifier means continuously connected to the output terminal of each of said first and second amplifier means, first switch means connected from the output terminal of said first amplifier means to the input terminal of said second amplifier means to selectively interconnect said first and second amplifier means, second switch means connected to the input terminal of said first amplifier means to selectively disable said first amplifier means from receiving input signals, and control means connected to said first and second switch means to control the operation thereof.

2. The combination recited in claim 1 wherein said first amplifier means has two input terminals for receiving input signals, said second switch means connected between said two input terminals to selectively short circuit said terminals wherein said first amplifier means receives no input signal.

3. The combination recited in claim 1 wherein said control means causes said first and second switches to be operative simultaneously whereby said first amplifier receives no input signal and produces an error signal and whereby said second amplifier means operates on said error signal produced by said first amplifier means to produce an error-representative signal, said differential amplifier arranged to produce no output signal in response to the concurrent application thereto of said error signal from said first amplifier means and said error representative signal from said second amplifier means.

4. The combination recited in claim 1 wherein said first amplifier means includes a plurality of amplifier circuits connected in cascade.

5. The combination recited in claim 1 wherein each of said first and second switch means includes at least one semiconductor device.

6. The combination recited in claim 1 wherein said differential amplifier includes temperature compensated constant current source means.

7. The combination recited in claim 1 including output means connected to said differential amplifier means, said output means including at least one emitter follower circuit.