CIRCUIT ARRANGEMENT FOR THE PRESENTATION OF WAVEFORMS ON VIEWING SCREENS UTILIZING RASTER DEFLECTION

• US 3,686,662 A
• Filed: 11/12/1970
• Issued: 08/22/1972
• Est. Priority Date: 11/12/1970
• Status: Expired due to Term

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Blixt S. Stefan, Dag Martin Andersson
• Inventors: Blixt, S. Stefan, Andersson, Dag Martin
• Primary Examiner(s): Caldwell, John W.
• Assistant Examiner(s): Curtis, Marshall M.
• Application Number:
  US05/088,924
• Time in Patent Office: 649 Days
• Field of Search: 340/324A,172.5 235/197,198
• US Class Current: 345/20
• CPC Class Codes: G01R 13/20 Cathode-ray oscilloscopes
• CPC Class Codes: G09G 1/162 for displaying digital inputs as analog magnitudes, e.g. curves, bar graphs, coordinate axes, singly or in combination with alpha-numeric characters cathode-ray oscilloscopes for displaying analog inputs, singly or in combination with alpha-numeric characters G01R13/20; television receiver circuitry for displaying supplementary, e.g. alpha-numeric, information H04N5/445
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

There is disclosed herein a sample and inexpensive circuit arrangement for presenting waveforms on viewing screens of the cathode ray type having a light spot, due to the electron beam, deflected in a television-like raster. The presentation of waveforms is achieved by means of a device that delivers the value of the differences between adjacent spaced y values in digital form simultaneously with the light spot sweeping over the viewing screen in the x direction. An interpolation means is connected to the device for forming values of equidistant xcoordinates intermediate the spaced adjacent y values such that they are spaced close enough together to provide the desired resolution in the x direction. A comparison circuit is connected to the interpolating means to compare the y values as formed and the pertinent position of the light spot in the y direction. Due to the comparison, a video signal is provided in accordance with logic criteria that makes it possible to present the desired waveform.

Claims

1. A circuit arrangement for presenting waveforms, each of said waveforms describing a first variable y as a function of a second variable x, each of said first and second variables being represented by a plurality of spaced points, each of said spaced points of an associated one of said first and second variables having a difference value, on a cathode ray type viewing screen comprising:

first means coupled to said viewing screen to simultaneously sweep a light spot having an intensity that may be modulated by a video signal over said viewing screen in the x and y directions with substantially different sweep frequencies to form a line raster to establish an imaginary coordinAte system for said waveform;

second means to provide sequentially in the order of the values of said second variable the digital value of the differences between the values of adjacent ones of said spaced points of said first variable simultaneously with said light spot sweeping over said viewing screen in said x direction;

third means including digital arithmetic means coupled to said second means to provide digital values for said first variable at equidistant x-coordinates intermediate said values of said adjacent ones of said spaced points of said first variable;

fourth means coupled to said first means to provide in digital form the position of said light spot on said viewing screen in said y direction;

fifth means coupled to said third and fourth means to digitally compare the digital output signals of said third and fourth means; and

sixth means coupled to said fifth means to provide said video signal in the form of either of two binary levels in accordance with predetermined logic criteria to intensity modulate said light spot and thereby present a waveform on said viewing screen.

2. A circuit arrangement according to claim 1, wherein said video signal provided by said sixth means causes said light spot to be lit when said output signal of said fourth means equals said output signal of said third means and when said output signal of said forth means is greater than said output signal of said third means for the latest value of said first variable but less than said output signal of said third means for the immediately preceding value of said first variable.

3. A circuit arrangement according to claim 1, wherein the faster of said different sweep frequencies defines the horizontal positions of said line raster and occurs in said x direction;

and said second means provides said digital value of the differences between the values of adjacent ones of said spaced points of said first variable between given levels in said y direction for presentation of one waveform and other different digital values of the differences between the values of adjacent ones of said spaced points of said first variable between other different levels in said y direction for presentation of other waveforms.

4. A circuit arrangement according to claim 1, wherein said third means provide said intermediate digital values for said first variable 2n times more often than said second means provides said digital value of the differences between the values of said adjacent ones of said spaced points of said first variable by accumulative addition of successive ones of said digital value of the difference between the values of said adjacent ones of said spaced points of said first variable, where n is an integer greater than zero.

5. A circuit arrangement according to claim 1, wherein said first means includes seventh means to produce a horizontal sync signal at the start of each horizontal line of said line raster;

and said fourth means includes a digital counter coupled to said seventh means to count said horizontal sync signal to provide in digital form the position of said light spot on said viewing screen in said y direction.

6. A circuit arrangement according to claim 1, wherein said third means includes a register having N +n stages, where n is an integer greater than zero and N is the number of bits in said digital values of the difference between the values of said adjacent ones of said spaced points of said first variables;

said fourth means includes a digital counter having at least M stages, where M is a integer less than the sum of the integer values of N and n;

said fifth means includes first logic circuitry coupled to the M most significant stages of said register and the M stages of said digital counter; and

said sixth means includes second logic circuitry coupled to said first logic circuitry to provide said video signal.

7. A circuit arrangement according to claim 6, wherein said third means further includes an adder having N + n stages coupled between said second means and said register, each of the n most significant stages of said adder receiving the most significant bit of said digital value of said difference between the values of said adjacent ones of said spaced points of said first variable and each of the remaining N stages of said adder receiving a different one of the remaining bits of said digital value of said difference between the values of said adjacent ones of said spaced points of said first variable, and each of the N + n stages of said adder being coupled to a different one of the N + n stages of said register to enable coupling digital values in two directions between said register and said adder.

8. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present one of said adjacent ones of said spaced points of said first variable, a first register coupled to said third means to store the complement of the digital value of the previous one of said adjacent ones of said spaced points of said first variable, and an adder coupled to said memory means and said first register to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.

9. A circuit arrangement according to claim 8, wherein said memory means includes N second shift registers, where N is the number of bits in said digital values of said adjacent ones of said spaced points of said first variable, each of said second shift registers including logic circuitry to circulate therein the contents thereof, and a third shift register having N inputs, each of said N inputs being coupled to a different one of said second shift registers.

10. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present one of said adjacent ones of said spaced points of said first variable, a register coupled to said third means to store the digital value of the previous one of said adjacent ones of said spaced points of said first variable, means coupled to said register to complement said stored digital value, and an adder coupled to said memory means and said means to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.

11. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the present and previous ones of said adjacent ones of said spaced points of said first variable, a register coupled to said memory means to store the digital value of the previous one of said adjacent ones of said spaced points of said first variable, means coupled to said register to complement said stored digital value, and an adder coupled to said memory means and said means to obtain the digital value of the difference between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced points of said first variable.

12. A circuit arrangement according to claim 1, wherein said second means includes memory means to provide the digital value of the differences between the digital value of said present one of said adjacent ones of said spaced points of said first variable and the digital value of said previous one of said adjacent ones of said spaced poinTs of said first variable.