READ ONLY MEMORY SYSTEM HAVING INCREASED DATA RATE WITH ALTERNATE DATA READOUT

• US 3,691,534 A
• Filed: 11/04/1970
• Issued: 09/12/1972
• Est. Priority Date: 11/04/1970
• Status: Expired due to Term

• Current Assignee: Andrew G. Varadi, Richard B. Rubinstein, Steven Radoff
• Original Assignee: Andrew G. Varadi, Richard B. Rubinstein, Steven Radoff
• Inventors: Rubinstein, Richard B., Radoff, Steven, Varadi, Andrew G.
• Primary Examiner(s): Konick, Bernard
• Assistant Examiner(s): Hecker, Stuart
• Application Number:
  US05/086,882
• Time in Patent Office: 678 Days
• Field of Search: 340/173R,172.5
• US Class Current: 365/78
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A permanent storage memory system comprises first and second memory units each having data stored thereon in different predetermined patterns. The outputs of each memory unit are connected to a common memory output. Timing signals are applied to each memory unit in reverse order and the selected data is transferred to the common memory output from one unit and then the other during the first and second of these signals, respectively. For each memory unit, data is blocked from the output during the period of the timing signal in which the data is not being transferred, thereby to enable ready combination of the data signals from each unit at the memory output. Data from each unit may be scanned in a predetermined sequence, that sequence being initiated from a location in that unit determined by an address signal applied to the unit. The selection of that initial memory location is performed by means of a shift register in combination with a logic unit. The latter receives an address signal and presets the shift register in accordance therewith.

Claims

1. A permanent storage memory system comprising first and second memory units each having an output node and information bits stored therein at a plurality of address stations in predetermined arrangements, sources of first and second timed signals, means effective to select an address station on each of said units, means effective to transfer to said output nodes of said first and second units, during said first and second timed signals respectIvely, data signals corresponding to the information bits stored at the respective selected address stations, data blocking means on said first and second units for placing said output nodes in the first and second units in a reference condition when actuated by said second and first timed signals, respectively, and means operatively connecting said output nodes, thereby to define a common memory output.

2. The memory system of claim 1, each of said memory units comprising a data section in which said information bits are stored and an intermediate point, said data sections each having an output terminal, said signal transferring means comprising means operatively connected between said data section output terminal and said intermediate point and effective when actuated to operatively connect said data section output terminal to said intermediate point, thereby to transfer an information bit to the latter, and output means operatively interposed between said intermediate point and said output node.

3. The memory system of claim 2, in which said data blocking means comprises a first switching device having a pair of output terminals respectively connected to said intermediate point and a reference point, and a control terminal operatively connected to one of said sources of said timed signals, said output means comprising a second switching device having its control terminal operatively connected to said intermediate point and one of its output terminals operatively connected to said output node, said first switching devices being effective when said one of said timed signals is applied thereto to operatively connect said intermediate point to said reference point and to establish said reference condition at said output node.

4. The memory system of claim 3, further comprising capacitance means operatively connected to said data section output terminals and to said signal transferring means, and means effective to precharge said capacitance means in said first and second memory units to a first level during said second and first timed signals respectively, and to either maintain said capacitance means at said first level or to discharge said capacitance means to a second level, depending on the information bit at said data section output terminal, during said first and second timed signals respectively.

5. The memory system of claim 2, in which said data section comprises a plurality of intersecting lines of first and second types, the intersection of one line of said first type and one line of said second type defining one of said address stations, said data section comprising a supplemental line of one of said first and second types having data stored therein in a unique predetermined pattern, means for selectively addressing each of said line of said one of said types, and means operatively connected between said data section output terminal and said addressing means and effective when said supplemental line is addressed to disable said addressing means.

6. The memory system of claim 5, in which data is stored at said address stations in one of two discrete logic conditions, all of said address stations in said supplemental line being of one of said logic conditions, and comprising logic means operatively connected to said supplemental line and switching means operatively connected to said logic means and effective when actuated to unconditionally place said output node in said reference condition, said logic means being effective when said supplemental line is addressed to actuate said switching means.

7. The memory system of claim 1, each of said memory units comprising a data section at which said information bits are stored, said data sections each having an output terminal, and further comprising capacitance means operatively connected to said data section and to said signal transferring means, and means effective to precharge said capacitance means in said first and second memory units to a first level during said second and first timed signals respectivelY, and to either maintain said capacitance means at said first level or to discharge said capacitance means to a second level, depending on the information bit at said data section output terminal, during said first and second timed signals respectively.