SYSTEM FOR THE DETECTION AND VALIDATION OF SIGNAL PEAKS

• US 3,693,028 A
• Filed: 09/30/1970
• Issued: 09/19/1972
• Est. Priority Date: 09/30/1970
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Richard L. Fussell
• Inventors: Fussell, Richard L.
• Primary Examiner(s): Forrer, Donald D.
• Assistant Examiner(s): Anagnos, L. N.
• Application Number:
  US05/076,905
• Time in Patent Office: 720 Days
• Field of Search: 307/232,235,247,260,261,264 328/31,109,110,115,116,117,60,61,62,132,150,151,203,206
• US Class Current: 327/58
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02

Abstract

A signal peak detection system is disclosed which in a preferred embodiment utilizes the initial actuation of one of a pair of regenerative threshold detectors by an input analog signal, the actuated detector providing threshold information to decision logic for initiating signal analysis processing at a suitable time prior to the occurrence of the signal peak. The system also includes storage units responsive to the respective states of the detectors, and gating circuits for providing an indication of the occurrence of an over-the-peak condition. Depending upon the nature of the input signal, such indication results either from the recovery of the detector initially actuated, or by the concurrent actuation of both detectors as reflected by the presence of output signals from the associated storage units. An over-the-peak output signal is generated by the system only when predetermined characteristics of the input signal have been validated by the decision logic.

Claims

1. A signal peak detection system for receiving an input pushpull electrical signal comprising first and second threshold detectors each having an input and an output terminal, the inphase and phase-inverted forms of said input signal being applied respectively to the input terminals of said threshold detectors, each of said detectors including an input current amplifying stage, first and second bistable means each having set and reset input terminals and an output terminal, means coupling the output terminals of said first and second detectors respectively to the set terminals of said first and second bistable means, a capacitor connecting said input terminal of each detector to its associated current amplifying stage, each of said input stages being normally in a conducting state and each of said first and second bistable means being in a reset state in the absence of said electrical signal, the degree of conduction of the input current amplifying stages being a function of the respective instantaneous amplitudes of said in-phase and phase-inverted forms of said electrical signal and the electrical charges on the capacitors associated therewith, one of said forms of input signal initially causing the input stage in said first detector to cease conduction, the other of said forms of input signal concurrently causing increased conduction in the input stage of said second detector and the charging of its associated capacitor, said first bistable means being switched from the reset state to the set state in response to the cessation of conduction of the input stage of said first detector, a plurality of AND gaTes each having a pair of input terminals and an output terminal, means coupling the output terminals of said first detector and said first bistable means to the respective input terminals of a first of said AND gates, means coupling the output terminals of said first and second bistable means to the respective input terminals of a second of said AND gates, means coupling the output terminals of said second detector and said second bistable means to the respective input terminals of a third of said AND gates, the concurrent presence of predetermined signal levels on the pair of input terminals of any one of said AND gates providing a gate output signal indicative of the attainment of a peak condition by said input signal.

2. A signal peak detection system as defined in claim 1 wherein said first and second bistable means are respectively first and second flip-flop circuits.

3. A signal peak detection system as defined in claim 2 wherein the amplitude of said input signal is at the threshold of the detector input stage, the passage of said input signal through its maximum absolute amplitude resulting initially in the return of the input stage of said first detector to its original conducting stage, said first flip-flop circuit being unaffected by the return of the input stage of said first detector to conduction and remaining in the set state, the signals appearing respectively on the output terminals of said first detector and said first flip-flop circuit being of said predetermined level, and being applied concurrently to the respective input terminals of the first of said AND gates to provide an output peak indication therefrom.

4. A signal peak detection system as defined in claim 2 wherein the amplitude of said input signal is substantially greater than the threshold of the detector input stage, the passage of said input signal through its maximum absolute amplitude resulting initially in the return of the input stage of said second detector to its normal state of conduction and the subsequent discharge of its associated capacitor, whereby said last-mentioned stage is driven to a nonconducting state, said second flip-flop circuit being switched from the reset state to the set state in response to the cessation of conduction of the input stage of said second detector, both said first and second flip-flop circuits being in the set state at this time, the signals appearing respectively on the output terminals of said first and second flip-flop circuits being of said predetermined level, and being applied concurrently to the respective input terminals of the second of said AND gates to provide an output peak indication therefrom.

5. A signal peak detection system as defined in claim 2 wherein each of said threshold detectors include an output current amplifying stage coupled to said input stage in a regenerative configuration, each of said stages having an input, an output and a control electrode, each of said capacitors being connected between a detector input terminal and the control electrode of the input stage associated with that detector, impedance means for coupling said input stage control electrode to said output stage output electrode, impedance means for coupling respectively the output electrodes of said stages to a source of supply potential, the input electrodes of said stages being connected in common to a source of reference potential, said output terminal of each of said detectors corresponding electrically to the output electrode of its output stage, and reset means comprising for each of said detectors the series combination of impedance means and a diode for coupling the control electrode of said input stage to a source of reset control current.

6. A signal peak detection system as defined in claim 5 wherein said current amplifying stages are transistors, and said input, output and control electrodes are respectively emitter, collector and base electrodes.

7. A signal peak detection system as defined in claim 6 further includIng decision logic means having first and second input terminals, a reset control terminal and a system output terminal, first and second OR gates each having a plurality of input terminals and an output terminal, means coupling the output terminals of said first and second OR gates respectively to the first and second input terminals of said decision logic means, means coupling the signals appearing respectively on the set terminals of said first and second flip-flop circuits to a pair of input terminals of said first OR gate, the signal levels appearing on the output terminals of said first OR gate being applied to said decision logic means for selectively initiating processing activity therein and terminating the generation of reset control current thereby, means for coupling said reset control terminal of said decision logic means to said reset means of each of said detectors and to the reset terminals of each of said first and second flip-flop circuits, the output terminals of said plurality of AND gates being coupled respectively to the input terminals of said second OR gate, the presence of a signal on an input terminal of said second OR gate allowing said gate to pass a peak indication signal to said decision logic means, said decision logic means providing at said system output terminal an output signal indicative of a valid detection.

8. A signal peak detection system as defined in claim 7 wherein said decision logic means comprises a third flip-flop circuit having set and reset terminals, inverter means coupling said first input terminal of said decision logic means to the reset terminal of said third flip-flop circuit, a first differentiating circuit coupled to said first decision logic input terminal, a first delay multivibrator having an input terminal coupled to said first differentiating circuit and a pair of output terminals for providing pulse outputs of opposite polarity and predetermined duration in response to a trigger pulse from said first differentiating circuit, fourth and fifth AND gates each having a pair of input terminals and an output terminal, a third OR gate having first, second and third input terminals and an output terminal, the output terminal of said third OR gate being coupled to the set terminal of said third flip-flop circuit, means coupling said second decision logic input terminal and one of said output terminals of said first delay multivibrator to the respective input terminals of said fourth AND gate, the output terminals of said fourth AND gate being coupled to said first input terminal of said third OR gate, a second differentiating circuit coupled to the other output terminal of said first delay multivibrator, a second delay multivibrator having an input terminal coupled to said second differentiating circuit and a pair of output terminals for providing pulse outputs of opposite polarity and predetermined duration in response to a trigger pulse from said second differentiating circuit, means coupling said second decision logic input terminal and one of said output terminals of said second delay multivibrator to the respective input terminals of said fifth AND gate, the output terminal of said fifth AND gate corresponding electrically to said system output terminal and being coupled to said second input terminal of said third OR gate, a third differentiating circuit coupled to the other output terminal of said second delay multivibrator, the output of said third differentiating circuit being coupled to said third input terminal of said third OR gate, the setting of said third flip-flop circuit in response to an output signal from said third OR gate causing said third flip-flop circuit to generate a reset control pulse on said reset control terminal, said reset pulse being applied concurrently to said second delay multivibrator to inhibit the operation thereof, and to the reset means of both said threshold detectors, and to the reset terminals of said first and second flip-flop circuits.