APPARATUS FOR INTERROGATING THE AVAILABILITY OF A COMMUNICATION PATH TO A PERIPHERAL DEVICE

• US 3,693,161 A
• Filed: 07/09/1970
• Issued: 09/19/1972
• Est. Priority Date: 07/09/1970
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Erwin A. Hauck, Jacob F. Vigil, William Chandler Price
• Inventors: Hauck, Erwin A., Price, William Chandler, Vigil, Jacob F.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/053,441
• Time in Patent Office: 803 Days
• Field of Search: 340/172.5
• US Class Current: 710/38
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405

Abstract

There is described a computer system in which one or more processors can interrogate, on command, the input/output system to determine whether communication paths are available to the respective peripheral units. The input/output system has one or more multiplexors which service a number of input/output channels, each channel having a peripheral control unit that controls one or more peripheral devices. Some peripheral devices are operated by more than one peripheral control unit and associated channel through a switching exchange. The input/output system, in response to an interrogation command executed by any of the processors and identifying a selected peripheral device, returns information to the processor indicating whether or not a communication path is available to the designated peripheral device and, if more than one channel is available, which multiplexor has a channel available to that device. The processor then can initiate an input/output operation between the particular unit and memory.

Claims

1. A computer system comprising memory means, a processor including an instruction register, data register means, and control means responsive to the contents of the instruction register for controlling the processor to execute each instruction in the instruction register, a plurality of peripheral units of different types adapted to send or receive data, each peripheral unit having a uniquely coded unit designation identifying the peripheral unit, a plurality of control units, each control unit controlling operation of at least one peripheral unit, means connecting each peripheral unit to at least one control unit, at least one multiplexing unit adapted to transfer data between selected ones of the control units and the memory means over a plurality of multiplexed data transfer channels, each control unit including means generating a Not Busy signal indicating when the control unit is not in use, means activated by said control means in the processor in response to a particular instruction in the instruction register of the processor for transferring a control word from the data register means in the processor to the multiplexing unit, the control word identifying a peripheral unit by its coded unit designation, decoding means in the multiplexing unit responsive to the unit designation provided by the control word received from the data register means for generating output signals identifying which if any of the control units associated with the multiplexing unit is connected to and controls the designated peripheral unit, means responsive to the output signals from the decoding means and the not busy signals from the control units for generating a binary coded output control signal that indicates if any of the control units identified by the output signals of the decoding means is not in use, and means in the multiplexing unit for transferring said output control signal to the data register means in the processor for storing the status of said output control signal in the processor.

2. Apparatus as defined in claim 1 further including means in the multiplexing unit responsive to said control word from the processor for transferring the peripheral unit designation portion of the coded word back to the data register means in the processor.

3. Apparatus for controlling transfer of data between a plurality of input/output units and main memory in a multiprocessor computer, comprising a plurality of processors, each processOr including data register means, an instruction register, and control means responsive to the contents of the instruction register for controlling the processor in accordance with the contents of the instruction register, a plurality of peripheral control units for controlling associated input/output units, each control unit being connected to and arranged to control one or more predetermined input/output units, a plurality of multiplexing units controlling transfer of data between main memory and said plurality of control units, a scan bus interconnecting each of the processors and the multiplexing units, the control means in any one of the processors in response to a predetermined setting of the instruction register of the corresponding processor transferring a control word from said data register means by the scan bus to all of the multiplexing units, the control word having a number identifying a particular input/output unit, each of the multiplexing units including decoding means responsive to the input/output unit number of the control word on the scan bus, the decoding means providing an output identifying which if any peripheral control units associated with the multiplexing unit is connected to the particular input/output unit identified by the number in the control word, and signaling means coupled to the output of the decoding means for signaling the processor over the scan bus if the output of the decoding means indicates that any peripheral control unit is connected to the particular input/output unit identified by the number in the control word.

4. Apparatus as defined in claim 3 wherein each control unit includes means generating a signal indicating when the control unit is in a Not Busy state, said signaling means including means responsive to the Not Busy signals for enabling said signaling means only if one of the control units connected to the designated input/output unit is in a Not Busy state.

5. Apparatus as defined in claim 4 wherein each multiplexing unit further includes means providing a signal identifying the particular multiplexing unit, means responsive to said output signal which indicates if any of the control units is not busy for coupling the signal identifying the particular multiplexing unit back to the processors by the scan bus.