THREE TRANSISTOR MEMORY CELL

• US 3,699,544 A
• Filed: 05/26/1971
• Issued: 10/17/1972
• Est. Priority Date: 05/26/1971
• Status: Expired due to Term

• Current Assignee: Joseph L. Mundy, Reuben E. Joynson
• Original Assignee: Joseph L. Mundy, Reuben E. Joynson
• Inventors: Joynson, Reuben E., Mundy, Joseph L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/146,969
• Time in Patent Office: 510 Days
• Field of Search: 340/173R,173AM,173DR,173FF,173CA 307/238,279
• US Class Current: 365/149
• CPC Class Codes: G11C 11/402 with charge regeneration individual to each memory cell, i.e. internal refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A three transistor dynamic memory cell is disclosed utilizing a voltage controlled capacitor to enhance signal coupling in the cell. In addition, the refreshing operation is greatly enhanced due to the configuration of the cell; viz. refreshing is achieved without an inverting amplifier, several cells can be refreshed simultaneously, and refreshing can occur while other operations are performed by the same cell.

Claims

1. An improved three transistor memory cell comprising:

firSt and second pairs of access lines;

first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines;

the gate of said first transistor forming a storage node for storing information in the form of electric charge;

the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon;

a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and

a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.

2. An improved memory cell as set forth in claim 1 wherein the drain electrode of said voltage variable capacitor comprises the drain of said first transistor.

3. An improved memory cell as set forth in claim 2 wherein the source-drain path of said third transistor is coupled between said storage node and the other of said first pair of access lines.

4. An improved memory cell as set forth in claim 1, wherein the drain electrode of said voltage variable capacitor comprises a separate drain electrode connected to one of said first pair of access lines.

5. An improved memory cell as set forth in claim 4 wherein the source-drain path of said third transistor is connected between said storage node and the junction of said first and second transistors.

6. An improved memory cell as set forth in claim 5 and further comprising a diode connecting said series connected first and second transistors to said one of said first pair of access lines.

7. An improved memory cell as set forth in claim 6 wherein said diode comprises a transistor having its gate and drain electrodes connected together.

8. An improved memory cell a set forth in claim 5 and further comprising a diode series connected between the source-drain paths of said first and second transistors, and wherein the source-drain path of said third transistor is connected between said storage node and the junction of said second transistor and said diode.

9. An improved memory cell as set forth in claim 8 wherein said diode comprises a transistor having its gate and drain electrodes connected together.