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THREE TRANSISTOR MEMORY CELL

  • US 3,699,544 A
  • Filed: 05/26/1971
  • Issued: 10/17/1972
  • Est. Priority Date: 05/26/1971
  • Status: Expired due to Term
First Claim
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1. An improved three transistor memory cell comprising:

  • firSt and second pairs of access lines;

    first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines;

    the gate of said first transistor forming a storage node for storing information in the form of electric charge;

    the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon;

    a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and

    a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.

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