THREE TRANSISTOR MEMORY CELL
First Claim
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1. An improved three transistor memory cell comprising:
- firSt and second pairs of access lines;
first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines;
the gate of said first transistor forming a storage node for storing information in the form of electric charge;
the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon;
a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and
a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.
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Abstract
A three transistor dynamic memory cell is disclosed utilizing a voltage controlled capacitor to enhance signal coupling in the cell. In addition, the refreshing operation is greatly enhanced due to the configuration of the cell; viz. refreshing is achieved without an inverting amplifier, several cells can be refreshed simultaneously, and refreshing can occur while other operations are performed by the same cell.
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Citations
9 Claims
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1. An improved three transistor memory cell comprising:
- firSt and second pairs of access lines;
first and second field effect transistors having their sourcedrain paths series connected across said first pair of access lines;
the gate of said first transistor forming a storage node for storing information in the form of electric charge;
the gate of said second transistor coupled to one of said second pair of access lines and controlled by signals thereon;
a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by signals thereon, for coupling signals to said storage node; and
a voltage variable capacitor, comprising a gate electrode and a drain electrode, for selectively coupling signals from one of said first pairs of access lines to said storage node.
- firSt and second pairs of access lines;
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2. An improved memory cell as set forth in claim 1 wherein the drain electrode of said voltage variable capacitor comprises the drain of said first transistor.
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3. An improved memory cell as set forth in claim 2 wherein the source-drain path of said third transistor is coupled between said storage node and the other of said first pair of access lines.
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4. An improved memory cell as set forth in claim 1, wherein the drain electrode of said voltage variable capacitor comprises a separate drain electrode connected to one of said first pair of access lines.
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5. An improved memory cell as set forth in claim 4 wherein the source-drain path of said third transistor is connected between said storage node and the junction of said first and second transistors.
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6. An improved memory cell as set forth in claim 5 and further comprising a diode connecting said series connected first and second transistors to said one of said first pair of access lines.
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7. An improved memory cell as set forth in claim 6 wherein said diode comprises a transistor having its gate and drain electrodes connected together.
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8. An improved memory cell a set forth in claim 5 and further comprising a diode series connected between the source-drain paths of said first and second transistors, and wherein the source-drain path of said third transistor is connected between said storage node and the junction of said second transistor and said diode.
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9. An improved memory cell as set forth in claim 8 wherein said diode comprises a transistor having its gate and drain electrodes connected together.
Specification