ANALOG CAPACITOR MEMORY WITH SLOW WRITE-IN AND FAST NONDESTRUCTIVE READ-OUT

• US 3,701,120 A
• Filed: 09/18/1969
• Issued: 10/24/1972
• Est. Priority Date: 09/18/1969
• Status: Expired due to Term

• Current Assignee: James M. Bartlemay, John M. Folline, Robert L. Charters, Thomas G. Donich
• Original Assignee: James M. Bartlemay, John M. Folline, Robert L. Charters, Thomas G. Donich
• Inventors: Charters, Robert L., Bartlemay, James M., Folline, John M., Donich, Thomas G.
• Primary Examiner(s): Konick, Bernard
• Assistant Examiner(s): Hecker, Stuart
• Application Number:
  US04/862,633
• Time in Patent Office: 1,132 Days
• Field of Search: 340/173R,173CA 320/1 307/246,109
• US Class Current: 365/45
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

An analog memory capable of write-in at a relatively low rate and independent, nondestructive read-out at a relatively high rate. A single write-in and read-out address logic is provided for as memory units are desired. Each memory unit includes a matrix of sample and hold microcircuits, each having an external storage capacitor, an isolation amplifier and independent input and output analog switching in response to vertical and horizontal write-in and read-out addressing.

Claims

1. An analog memory system comprising:

a. a memory unit including a plurality of memory cells, each of said cells comprising a sample and hold circuit having an input terminal, a write-in address terminal, a read-out address terminal, and an output terminal and including a first analog switch having signal and control inputs, and an output, means coupling said input terminal to said signal input of said first analog switch, first means coupling said write-in address terminal to said control input of said first analog switch, an energy storage means connected to the output of said first analog switch, a second analog switch having signal and control inputs, and an output, an isolation amplifier coupling said energy storage means to said signal input of said second analog switch, second means coupling said read-out address terminal to said control input of said second analog switch, and third means coupling said output of said analog switch To said output terminal, said sample and hold circuit being operative to sample an analog signal at its input terminal when a write-in control signal is supplied to its write-in address terminal, to store the sampled signal during any subsequent interval, and to present the sampled signal to its output terminal when a readout control signal is supplied to its read-out address terminal, b. means coupling an analog signal to the input terminal of each memory cell, c. means summing the signals appearing on the output terminals of said memory cells to provide an output signal, d. write-in address logic means furnishing write-in control signals to said write-in address terminals of said plurality of memory cells at a relatively low repetition rate, and e. read-out address logic means furnishing read-out control signals to said read-out address terminals of said plurality of memory cells at a relatively high repetition rate.

2. The analog memory as recited in claim 1, wherein said first and second analog switches, said isolation amplifier, and said first and second coupling means of each sample and hold circuit comprise an integrated circuit, and said energy storage means includes a discrete capacitor connected thereto.

3. The analog memory as recited in claim 1 wherein:

a. said plurality of memory cells are arranged in a matrix of vertical and horizontal rows, b. said write-in control signals comprise vertical and horizontal write-in address signals, both of which must be supplied to each of said memory cells for said cell to sample data, wherein said first means coupling said write-in address terminal to said control input of said first analog switch in each of said sample and hold circuits comprises a first gating circuit, and c. said read-out control signals comprise vertical and horizontal read-out address signals, both of which must be supplied to each of said memory cells for said cell to output the sampled data, wherein each of said second means coupling said read-out address terminal to said control input of said second analog switch comprises a second gating circuit.

4. The analog memory as recited in claim 3 wherein said write-in address logic means includes:

a. a vertical ring counter producing said vertical write-in address signals and stepped at said relatively low repetition rate, and b. a horizontal ring counter producing said horizontal write-in address signals and stepped by said vertical ring counter, so that said matrix of memory cells is addressed in a sequential manner.

5. The analog memory as recited in claim 4 wherein said read-out address logic means includes:

a. a vertical ring counter producing said vertical read-out address signals and stepped at said relatively high repetition rate, and b. a horizontal ring counter producing said horizontal read-out address signals and stepped by said vertical ring counter, so that said matrix of memory cells is sequentially addressed for read-out.

6. The analog memory as recited in claim 3, further comprising:

a. a plurality of said memory units, each of said memory units having a single analog signal input terminal and a single sampled analog data output terminal, b. means coupling said analog signal to the analog signal input terminal of each of said memory units, c. a vertical ring counter and a horizontal ring counter included in said write-in address logic means, said vertical ring counter being stepped at said relatively low repetition rate and producing said vertical write-in address signals, said horizontal ring counter being stepped by said vertical ring counter and producing said horizontal write-in address signals, and d. means coupling the vertical and horizontal write-in address terminals of the corresponding memory cells in said plurality of memory units in parallel.

7. The analog memory as recited in claim 6, further comprising:

a. a vertical ring counter and a horizontal ring counter included in said read-out address logic means, said vertical ring counter being stepped at said relatively high repetition rate and producing said vertical read-out address signals, said horizontal ring counter being stepped by said vertical ring counter and producing said horizontal read-out address signals, and b. means coupling the vertical and horizontal read-out address terminals of the corresponding memory cells in said plurality of memory units in parallel.

8. The analog memory as recited in claim 7 wherein said first and second analog switches, said isolation amplifier and said first and second gating circuits of each said sample and hold circuit comprise an integrated circuit, and said energy storage means includes a discrete capacitor connected thereto.

9. The analog memory as recited in claim 7, further comprising:

a. counter means included in said write-in address logic means which produces a first series of pulses operative to step said vertical counter, and a second series of pulses which occur in a predetermined sequence in synchronism with said first series of pulses, b. a plurality of memory control logic means, each being interposed between said horizontal ring counter and one of said plurality of memory units, each additionally having a control input terminal and being operative to pass said horizontal write-in address signals upon the occurrence of a signal at said control input terminal, and c. means coupling one of said second series of pulses to the control input terminal of each of said plurality of memory control logic means so that the plurality of memory units are addressed for write-in in a predetermined sequence.

10. The analog memory as recited in claim 9 wherein:

a. said counter means produces a third series of pulses which occur at a repetition rate which is a multiple of the repetition rate of said first series of pulses, and b. each of said memory control logic means includes a second control input terminal therefor having said third series of pulses connected thereto, each of said memory control logic means being selectively operative to pass said horizontal write-in address signals in response to a predetermined combination of said pulses at the first and second control input terminals thereof.

11. The analog memory as recited in claim 9, wherein said analog signal coupling means includes:

a. a plurality of input sample and hold circuits each having an input terminal, a control terminal, and an output terminal, each of said input terminals being connected to said analog signal input, and each of said output terminals being connected to one of said plurality of memory units, b. each of said input sample and hold circuits being operative to sample said analog signal input for a period of time determined by the presence of a signal on its control input, and c. means coupling one of said second series of pulses to each control terminal of said plurality of input sample and hold circuits.

12. The analog memory as recited in claim 11, wherein each of said means coupling said second pulse series includes a monostable multivibrator.

13. The analog memory as recited in claim 9, further comprising:

a. a clock means included in said read-out address logic means which produces a fourth series of pulses operative to step said vertical counter in said read-out address logic means, b. a second counter in said read-out address logic means which is stepped by the output of said horizontal ring counter therein and which produces a fifth series of pulses which occur in a predetermined sequence in synchronism with the output pulses of said horizontal ring counter, c. a plurality of memory control logic means, each being interposed between said horizontal ring counter and one of said plurality of memory units, each additionally having a control input terminal and being operative to pass the horizontal read-out address signals upon the occurrence of a signal at said control input terminal, and D. means coupling one of said fifth series of pulses to the control input terminal of each of said plurality of memory control logic means so that the plurality of memory units are addressed for read-out in a predetermined sequence.

14. The analog memory as recited in claim 13, further comprising:

a. delay means having said fourth series of pulses connected thereto, b. a plurality of output sample and hold circuits, each of said circuits including an input terminal, an output terminal, and a control terminal, each of said input terminals being connected to the output terminals of a corresponding memory unit and each of said output terminals serving as an output terminal for the analog memory, c. each of said output sample and hold circuits being operative to sample the sampled analog data from its corresponding memory unit when a signal is present on its control input, and d. means coupling the delayed pulses from said delay means to the control terminals of each of said output sample and hold circuits.

15. The analog memory as recited in claim 13, wherein:

a. said second counter means produces a sixth series of pulses which occur at a given repetition rate, the repetition rate of said fifth series of pulses being a multiple of the repetition rate of said sixth series of pulses, and each of said memory control logic means in said read-out address logic means includes a second control input terminal having said sixth series of pulses connected thereto, each of said memory control logic means being selectively operative to pass said horizontal read-out address signals in response to a predetermined combination of said pulses at said first and second control input terminals thereof.

16. The analog memory as recited in claim 15 wherein said first and second analog switches, said isolation amplifier, and said first and second gating circuits of each said sample and hold circuit comprise an integrated circuit, and said energy storage means includes a discrete capacitor connected thereto.