FINE & COARSE SYNCHRO SERVOMOTOR CONTROL INCLUDING A DUAL SIN/COSINE TO DC CONVERTER

• US 3,701,936 A
• Filed: 12/10/1971
• Issued: 10/31/1972
• Est. Priority Date: 12/10/1971
• Status: Expired due to Term

• Current Assignee: Kenneth G. Martin, Paul A. Seuferer
• Original Assignee: Kenneth G. Martin, Paul A. Seuferer
• Inventors: Martin, Kenneth G., Seuferer, Paul A.
• Primary Examiner(s): T. E. Lynch
• Application Number:
  US05/206,603
• Time in Patent Office: 326 Days
• Field of Search: 318/595,654,661
• US Class Current: 318/595
• CPC Class Codes: G05D 1/042 specially adapted for aircraft
• CPC Class Codes: G05D 3/1436 with fine or coarse devices

Abstract

Dual-synchro coarse and fine error signals definitive of the discrepancy between a selected condition and that being experienced are converted by static means to a linear DC control signal. Linearization means implementing the control function 1 cos theta + sin theta are employed as concerns the fine error analog input signal, and the coarse error analog input signal is employed for switching functions which occur only at zero error and control extremes, thus obviating control discontinuities, transients, and sudden changes in control linearity.

Claims

1. Control signal development means for developing a linear DC error output signal from an angular error analog input signal source, said input signal source providing an error signal output proportional to the discrepancy between a condition command and an experienced condition, said error signal input comprising first, second, third, and fourth signals, said first and second signals comprising a carrier signal with amplitude modulation proportional respectively to sin theta and cos theta , where theta is an error analog angle and with respective opposite carrier phase for values of theta reflecting experienced conditions respectively above and below said commanded condition, said third and fourth input signals exhibiting sinusoidal and cosinusoidal amplitude modulations at a rate 1/N where N is the cyclic rate of said first and second signals, means for converting said first, second, third, and fourth error signals to a single linear DC output control signal comprising means for demodulating said first and second signals, signal conversion means receiving said demodulated first and second signals and a predetermined direct current signal source and developing therefrom a unipotential DC output signal proportional to the control function 1 - cos theta + sin theta , an output terminal, and means for selectively inverting the polarity of the output from said signal conversion means as applied to said output terminal as a function of the carrier phase of said first input signal.

2. Means as defined in claim 1 wherein said first and second and said third and fourth ones of said input signals defining said angular error analog input signal compriSes the respective paired outputs of first and second differential resolvers the stator windings of which are connected to respective ones of first and second three-wire synchro signal sources definitive of said experienced condition and the rotor windings of which are selectively rotatably positionable with respect to the stator windings by an angular degree definitive of said commanded condition.

3. Means as defined in claim 1 further comprising means for limiting the output of said signal conversion means as applied to said output terminal, means for demodulating said third input signal, limiter override signal development means responsive to said demodulated third input signal to develop an output of predetermined magnitude for amplitudes of said third input signal in excess of a predetermined level, means for combining said override signal with the output of said signal conversion means as applied to said means for limiting, and the magnitude of said limiter override signal being in excess of the limiting threshold of said means for limiting.

4. Means as defined in claim 2 further comprising means responsive to said limiter override signal to inhibit said polarity inversion of the output of said signal conversion means.

5. Means as defined in claim 4 wherein said means for inhibiting comprises gating means receiving the output of said high gain demodulator and providing an activating output to said first and second switch means in the absence of an inhibiting signal input thereto, said inhibiting signal input comprising the output of means to derive the absolute value of the output from said limiter override signal development means.

6. Means as defined in claim 4 wherein said predetermined DC source signal as utilized in said signal conversion means comprises the output from means for converting the carrier excitation source for said first, second, third, and fourth input signals to a direct current voltage.

7. Means as defined in claim 4 wherein said limiter override signal development means comprises a high gain dead-zone amplifier receiving said demodulated third input signal as an input thereto.

8. Means as defined in claim 7 wherein said means for polarity inversion comprises a high gain demodulator means receiving said first input signal and developing an output of predetermined magnitude in response to said input signal exhibiting a first phase and zero output in response to said first input signal exhibiting a phase opposite said first phase, said polarity inversion means being responsive to said predetermined magnitude output of said high gain demodulator to effect said polarity inversion of the output of said signal conversion means.

9. Means as defined in claim 8 wherein said signal polarity inversion means comprises a first switch means, a first inverting amplifier serially connected between the output of said signal conversion means and said first switch means, a second switch means, a second inverting amplifier serially connected between the output of said first inverting amplifier and said second switch means, said first and second switch means being responsive to zero output from said high gain demodulator to connect the output of said first inverting amplifier to said output terminal and being responsive to said predetermined magnitude output from said high gain demodulator to connect the output from said second inverting amplifier to said output terminal.

10. Means as defined in claim 9 wherein said predetermined magnitude output from said dead-zone amplifier is developed in response to said fourth input signal amplitude modulation being proportional to an angular error corresponding to less than one-third cycle of the amplitude modulation components of said first and second input signals.

11. Means as defined in claim 10 wherein each of said demodulating means has applied thereto a demodulator drive input signal having a frequency and phase corresponding to that of said fourth input signal.

12. Means as defined in claim 11 whErein each of said signal demodulating means provides an output signal of amplitude proportional to that of the amplitude modulated carrier input signal thereto and of a polarity corresponding to the phase of the carrier signal applied thereto.