MEMORY EXPANSION ARRANGEMENT IN A CENTRAL PROCESSOR

• US 3,703,708 A
• Filed: 05/12/1971
• Issued: 11/21/1972
• Est. Priority Date: 05/12/1971
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: Foster James Harold
• Inventors: FOSTER JAMES HAROLD
• Application Number:
  US05/142,649
• Time in Patent Office: 559 Days
• US Class Current: 711/2
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

The memory is divided into a program block and a data block with identical addresses for the two blocks, and a '"'"''"'"''"'"''"'"'paging'"'"''"'"''"'"''"'"' technique is used to select the appropriate block. The computer has an operation cycle for the execution of each instruction, the cycle being divided into intervals designated bit times. The first bit time of each cycle is used to read a program instruction word, and for some of the instructions a given other bit time of the cycle is used to read the contents of the operand address of the instruction. The paging technique comprises always reading a word from the program block during the first bit time, and during the other given bit times, for those instructions requiring reading the contents of the operand address, selecting either the program block or the data block depending upon the operation code. This permits operand addresses designating literals to be in the program block, while the principal data base is placed in the data block. In particular a transfer instruction does not have an operand address, but is used to take an address from the accumulator and read the contents thereof from the data block. To permit a similar operation for words in the program block, for example during a memory dump, a fetch instruction produces operations identical to those of the transfer operation, except that the contents of the address in the accumulator are obtained from the program block.

Claims

1. In a digital data processing system having a central processing unit and a memory;

wherein the memory comprises a plurality of word stores for program words and data words, the program words having a first part for an operation code and a second part for an operand, a memory input register for addresses designating the individual word stores, access means connected to read out a word from a store corresponding to the address in the memory input register and to supply signals representing the word to a set of memory output conductors;

wherein the central processing unit comprises memory output register means, an accumulator, an instruction register including an operation code decoder, arithmetic circuits, store registers, and interconnections among them and to the memory input register and memory output conductors, a clock, and operation cycling means driven by the clock to provide operation cycles comprising sequential states;

instruction reading means effective during a first state of each operation cycle using said access means to read out one program word from memory with the operation code into the instruction register and the operand into the memory output register means, means using the arithmetic circuits to perform an operation designated by the operation code, which for some operation codes includes data reading means effective during a subsequent state of the operation cycle for placing a data word address into the memory input register and using the access means to read out a corresponding data word into the memory output register means, and means effective during the operation cycle to place an address of a program word into the memory input register for the next operation;

the improvement wherein the memory is divided into a program block and a data block with identical addresses, wherein said access means includes program block addressing means and data block addressing means connected from the memory input register respectively to the program block and the data block, block selection means comprising first means and second means, the first means has inputs connected to outputs of the operation cycling means and instruction register and an output connected to actuate the program block addressing means during said first operation state and also during said subsequent operation state with given operation codes, the second means has inputs connected to outputs of the operation cycling means and instruction register and an output connected to actuate the data block addressing means during said subsequent operation state with other operation codes, so that said instruction readiNg means uses the first means to read program words from the program block, and said data reading means used the first means with said given operation codes to read data from the program block and the second means with said other operation codes to read data words from the data block.

2. In a digital data processing system, the combination as claimed in claim 1, wherein said given operation codes include a fetch operation code (OPB) and said other operation codes include a transfer operation code (OP3), gating means connected from the outputs of the accumulator to inputs of the memory input register actuated responsive to either the fetch or the transfer operation code (OP3 OPB+OP3T) during the operation cycle between said first state and said subsequent state to place a data word address into the memory input register.

3. In a digital data processing system, the combination as claimed in claim 1, wherein the memory addresses use a numbering system having a first and a second part for each address, memory address decoding means coupled to the output of said memory input register with the output of the decoding means having a first and a second group of address conductors for the two parts respectively, a plurality of memory drivers having inputs from the first group of conductors and a plurality of memory switches having address inputs from the second group of conductors each word of memory being selected by a unique combination of a driver and a switch;

wherein said memory drivers are divided into two blocks comprising respectively the program block addressing means and the data block addressing means, the outputs of each block of memory drivers being connected only to the corresponding block of memory;

wherein each memory driver further includes a pulse input and means responsive to a pulse on that input to actuate the driver to thereby read a word from memory in accordance with the address inputs which select one memory driver and one memory switch, and said block selection means further having inputs from the clock to enable the selected first means or second means to supply a signal on the pulse leads of the drivers of the program block or data block respectively.

4. In a digital data processing system, the combination as claimed in claim 3, wherein at least one of said memory drivers is connected to the clock and the address decoding means so that it may be selected independently of the block selection means to select corresponding memory addresses independently of the operation code.

5. In a digital data processing system, the combination as claimed in claim 3, wherein said first means and second means each includes pulse amplifier means, each having connections to a common memory-actuation clock pulse output (CPM) of the operation cycling means and each having a control input from logic means having inputs from the operation cycling means and from the instruction register and operation code decoder.

6. In a digital data processing system, the combination as claimed in claim 5, wherein at least one of said memory drivers is connected to the clock and the address decoding means so that it may be selected independently of the block selection means to select corresponding memory addresses independently of the operation code.

7. In a digital data processing system having a clock, a central processing unit and a memory, wherein the clock comprises means to generate recurring clock pulses on clock conductors in clock periods;

wherein the memory comprises a program block having a plurality of program word stores for storing the respective program words, a data block having a plurality of data word stores for storing respective data words, there being a fixed maximum number of bit positions in each word, with first (bits 1-

     4) and second (bits 5-

     20) parts comprising respective mutually exclusive bit positions of the words, each program word having an operation code as the first part and an operand aS the second part, a memory input register for storing an address, memory drivers and memory switches having address inputs from the memory input register and outputs coupled to said word stores to select one corresponding to the address in the memory input register, means including a pulse on a clock conductor coupled to inputs of the memory driver to actuate the memory, memory output means coupled to the word stores to receive the word from the selected store upon actuation of the memory, and supply it as signals on a set of memory output conductors;

wherein the central processing unit comprises an operation cycle counter (BTC), an address register, an instruction register, a first accumulator (AA), a second accumulator (AB), a store register (SA), and arithmetic circuits;

the operation cycle counter (BTC) comprises bistable devices, counting and logic circuits interconnected to provide N operation states with an output for each state, including a first, a second, and successive states up to the Nth state, the operation cycle counter being coupled to the clock and to the operation code decoder to change the state once each clock period advancing to the next state during an operation and resetting to the first state at the end of an operation;

the arithemtic circuits comprise gating and logic circuits interconnecting said registers, with connections from the clock, operation cycle counter and operation code decoder to perform operations during specified operation states in accordance with the output of the operation code decoder, said operations including transferring words between registers and other logical functions;

the instruction register comprises bistable devices having inputs coupled via gating circuits to the memory output conductors for the first part of a word, the last said gating circuits having a connection to the operation cycle counter to place the operation code of a program word in the instruction register during said first operation state, and the instruction register including an operation code decoder connected to outputs of its bistable devices with an individual output from the decoder for each operation code;

the address register comprises bistable devices for storing an address of the program block and counting circuits with connections to the operation cycle counter to advance one count during each occurrence of the first operation state, and arithmetic circuit connections to selectively advance one count during certain operations, and gating means to transfer the contents of the address register to the memory input register before the end of each operation;

the first accumulator comprises bistable devices having inputs coupled to the memory output conductors to receive and store every word selected upon operation of said means to actuate the memory, the first accumulator having outputs coupled via gating means to the memory input register and to the address register to transfer the second part of the word as an address in accordance with the operation code, and the outputs being also coupled to other of the arithmetic circuits for operations in accordance with the operation code;

the second accumulator comprises bistable devices having inputs and outputs interconnected via the gating and logic circuits of the arithmetic circuits to the other registers and the memory output conductors to receive, modify, and supply words in accordance with the operation specified on the output of the operation code decoder;

the store registers comprise bistable devices coupled to the memory input means and memory output means with individual address;

the system being operative beginning each operation with an address of the program block in the memory input register and reading the corresponding word from its store during the first operation state (BR1) into the first accumulator and the first part of the word into the instruction register;

performing operations during successive operation states in accordance With the operation code in the instruction register decoded by the operation code decoder, some operations including placing an address into the memory input register during the second operation state (BT2) and actuating the memory during the third operation state (BT3) to read the word into at least one of said accumulators, and every operation including placing the program address word from the address register into the memory input register for the next operations;

the improvement wherein the memory drivers are divided into a group for the program block of memory and a group for the data block of memory with drivers in the two groups having identical address inputs, wherein the memory switches are common to both memory blocks;

first means having inputs connected to outputs of the operation cycle counter and instruction register and an output connected to actuate the group of memory drivers for the program block during said first operation state and also during said third operation state with given operation codes, and second means having inputs connected to outputs of the operation cycle counter and instruction register and an output connected to actuate the group of memory drivers of the data block during said third operation state with other operation codes, so that said reading of a word during the first operation state uses said first means, and said actuating the memory during the third operation state to read the word makes use of said first means with said given operation codes and makes use of said second means for said other operation codes.

8. In a digital data processing system, the combination as claimed in claim 7, wherein said given operation codes include a fetch operation code (OPB) and said other operation codes include a transfer operation code (OP3T), gating means connected from the outputs of the second accumulator to inputs of the memory input register actuated responsive to either the fetch or the transfer operation code during said second operation state to place a data word address into the memory input register.

9. In a digital data processing system, the combination as claimed in claim 7, wherein said first means and said second means each include pulse amplifier means having outputs connected to inputs of the memory drivers for the corresponding memory block, the pulse amplifying means having a common pulse input to said clock conductor for actuating the memory, and control inputs from logic circuits which determine the selection of the appropriate block.

10. In a digital data processing system, the combination as claimed in claim 9, wherein said logic circuits include connections to the outputs of the operation cycle counter and the instruction register and operation code decoder, connected so that the control input of the pulse amplifier means for the program block is enabled during said first operation state, and during the third operation state for said given operation codes, and the control input of the pulse amplifier means for the data block is enabled by its control input during the third operation state for said other operation codes.

11. In a digital data processing system, the combination as claimed in claim 10, wherein said operation codes include a fetch code, wherein the operation code decoder has one of its outputs true for both the transfer and fetch operation codes, and this output is connected to the apparatus of the central processing unit to select an address from the second accumulator during the second operation state and place it into the memory input register, and to perform other functions common to these two operation codes;

and wherein the logic circuits of said first means and second means include connections from the last said output of the operation code decoder and also directly from one instruction register bistable device to distinguish between the transfer and fetch operation codes so that the program block pulse amplifying means is enabled for the fetch operation during the third oPeration state, and the pulse amplifying means for the data block is enabled for the transfer operation code.

12. In a digital data processing system, the combination as claimed in claim 11, wherein at least one of said memory drivers has an input connected directly to said clock conductor to actuate the memory, so that it is actuated for its address independently of said first means and second means, and wherein the address input means for this driver includes a connection to the operation cycle counter to address it only during the third operation state.