DIGITAL PRF FILTER

• US 3,705,358 A
• Filed: 08/09/1971
• Issued: 12/05/1972
• Est. Priority Date: 08/09/1971
• Status: Expired due to Term

• Current Assignee: Edward Collins IV, Weldon W. Bauman
• Original Assignee: Edward Collins IV, Weldon W. Bauman
• Inventors: Bauman, Weldon W., Collins, Edward IV
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US05/171,817
• Time in Patent Office: 484 Days
• Field of Search: 328/109,110,112,138,140 307/232-234
• US Class Current: 327/38
• CPC Class Codes: H03H 17/02 Frequency selective networks digital computers for complex mathematical operations G06F17/10

Abstract

A pulse repetition frequency (PRF) filter circuit for selectively passing pulse trains over a wide bandwidth. The filter circuit utilizes the pulse repetition interval (PRI) between the first and second pulses in a pulse train to gate the third pulse with a gating signal which anticipates the third pulse at the PRI of the first and second pulses. A first pulse from an input pulse train is delayed respectively by first and second fixed delay lines, and then triggers a circuit to develop a first sawtooth wave pattern over a time period 2T. A second pulse from the input pulse train is delayed by only the first delay line, and then triggers a circuit to develop a second sawtooth wave pattern over a time period of T. The second sawtooth wave pattern has a slope twice the slope of the first sawtooth wave pattern. The relationship between the first and second sawtooth wave patterns is such that the point when the amplitudes of both patterns are equal defines the PRI of the pulse train as indicated by the first and second pulses. A comparator circuit compares the amplitudes of the first and second sawtooth wave patterns, and when the amplitudes are equal develops a gating signal which anticipates a third and undelayed pulse at the PRI of the pulse train as indicated by the first and second pulses. The PRF filter circuit filters pulse trains on a random, first-come, first-served basis, and the circuit is timeshared equally among incoming pulse trains within the bandwidth of the circuit.

Claims

1. A system for producing an indication of the timing interval between first and second input pulses in a pulse train and for utilizing the indicated timing interval to gate a third pulse in the pulse train and comprising:

a. an input means for receiving input pulses;

b. first timing means for generating a first set of electrical signals having a value which changes at a first predetermined rate;

c. second timing means for generating a second set of electrical signals having a value which changes at a second predetermined rate greater than said first predetermined rate;

d. first actuation means for causing said first timing means to commence generating said first set of electrical signals upon the receipt of the first input pulse by the first actuation means;

e. second actuation means for causing said second timing means to commence generating said second set of electrical signals upon the receipt of the second input pulse by the second actuation means;

f. comparator means coupled to said first and second timing means for producing an output signal upon the occurrence of a predetermined relationship between said values associated with said first and second sets of electrical signals, said output signal being indicative of the timing interval between said first and second input signals;

g. means, including said comparator means, for developing a gating signal for a third pulse in the pulse train at the timing interval, as indicated by the output signal of said comparator means, after the receipt by said input means of the second input pulse; and

h. means for gating the third pulse if it arrives in coincidence with said developed gating signal.

2. Apparatus as set forth in claim 1 wherein said developing means includes:

a. a first delay means, connected between said input means and said first actuation means, for delaying the first pulse for a first given period of time after receipt by said input means before directing the first pulse to said first actuation means; and

b. a second delay means, connected between said input means and said second actuation means, for delaying the second pulse for a second given period of time after receipt by said input means before directing the second pulse to said second actuation means.

3. Apparatus as set forth in claim 2 wherein said means for delaying the second pulse for a second period of time includes means for delaying the second pulse for a period of time which is half as long as said first period of time.

4. Apparatus as set forth in claim 3 wherein said first delay means and said second delay means include a common delay line with said first actuation means receiving the first pulse from the end of the common delay line and said second actUation means receiving the second pulse from the middle of the common delay line.

5. Apparatus as set forth in claim 4 wherein said gating means includes an AND gate having input connections from said input means, said first timing means, said second timing means, and said means for developing a gating signal.

6. Apparatus as set forth in claim 3 wherein:

a. said first timing means includes means for developing a first ramp function having a given slope;

b. said second timing means includes means for developing a second ramp function having a slope greater than the slope of said first ramp function; and

c. said comparator means includes means for detecting when the amplitude of said second ramp function has a predetermined relationship to the amplitude of said first ramp function.

7. Apparatus as set forth in claim 6 wherein said second timing means includes means for developing a ramp function having a slop twice the slope of said first ramp function.

8. Apparatus as set forth in claim 7 wherein said first delay means and said second delay means include a common delay line with said first actuation means receiving the first pulse from the end of the common delay line and said second actuation means receiving the second pulse from the middle of the common delay line.

9. Apparatus as set forth in claim 8 wherein said gating means includes an AND gate having input connections from said input means, said first timing means, said second timing means, and said means for developing a gating.

10. Apparatus as set forth in claim 1 wherein:

a. said first timing means includes means for developing a first ramp function having a given slope;

b. said second timing means includes means for developing a second ramp function having a slope greater than the slope of said first ramp function; and

c. said comparator means includes means for detecting when the amplitude of said second ramp function has a predetermined relationship to the amplitude of said first ramp function.

11. Apparatus as set forth in claim 10 wherein said second timing means includes means for developing a ramp function having a slope twice the slope of said first ramp function.