A. C. STABLE STORAGE CELL

• US 3,706,891 A
• Filed: 06/17/1971
• Issued: 12/19/1972
• Est. Priority Date: 06/17/1971
• Status: Expired due to Term

• Current Assignee: Nicholas M. Donofrio, Richard H. Linton
• Original Assignee: Nicholas M. Donofrio, Richard H. Linton
• Inventors: Linton, Richard H., Donofrio, Nicholas M.
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): Hary, R. E.
• Application Number:
  US05/154,104
• Time in Patent Office: 551 Days
• Field of Search: 307/238,205,221C,251,279,304 340/173CA,173R
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

This specification discloses an A.C. stable or stored charge storage cell for use in monolithic memories. The cell includes a capacitor that couples a drive line to a sense line. The capacitance of this capacitor is voltage dependent so that when charged it provides a high capacitance to couple signals on the drive line to the sense line and when discharged it provides a low capacitance to prevent the coupling of signals from the drive line to the sense line.

Claims

1. In a stored charge storage cell addressed by the selection of a plurality of lines out of a grid of addressing lines and having a capacitor as its storage element, the improvement comprising:

a. a voltage dependent capacitor coupling the first of the selection lines to a second of the selection lines to control the passage of signals between the two lines, said capacitor having two states of capacitance, one low capacitance state when a small voltage is impressed across the capacitor and a second high capacitance state when a large voltage is impressed across the capacitor; and

b. data writing means for controlling the potential across said voltage dependent capacitor to place said capacitoR in its low capacitance state to store one state of binary data on its high capacitance state, to store the other state of binary data whereby the said two lines are coupled or decoupled depending on the binary path stored in the capacitor, said date writing means including a first field effect transistor with its gate coupled to a third of the selection lines, one of its gated terminals coupled to the first of the selection lines and the other of its gated terminals coupled through the voltage dependent capacitor of the second of the selection lines so that the potential on the third of the selection lines controls whether the voltage dependent capacitor is charged or not by a potential existing between the first and second of the selection lines;

a source of reference potential; and

second and third field effect transistors with their gated terminals connected in series between the first of the addressing lines and a source of fixed reference voltage to form a discharge path between the first of the addressing lines and the source of reference potential when both the second and the third transistors are rendered conductive, the gate of the third field effect transistor being connected directly to the second of the addressing lines so that the third transistor is always rendered conductive to an interrogating pulse on the second of the addressing lines while the gate of the third transistor is connected through the voltage sensitive capacitor to the second of the addressing lines so that the second transistor is rendered conductive only when the voltage sensitive capacitor is in its high capacitance state whereby charging and discharging of the potential on the first of the addressing lines indicates what state has been stored in the storage cell by the placing of the voltage sensitive capacitor in its low or high voltage state.