LATCHING AND CONTROL CIRCUIT FOR CARRIER DETECTION

• US 3,711,777 A
• Filed: 09/16/1971
• Issued: 01/16/1973
• Est. Priority Date: 09/16/1971
• Status: Expired due to Term

• Current Assignee: Robert M. Tink
• Original Assignee: Robert M. Tink
• Inventors: Tink, Robert M.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US05/181,166
• Time in Patent Office: 488 Days
• Field of Search: 178/88 325/64,320,322,323,364,478 340/171R,172 328/139,140,150,151 329/178
• US Class Current: 375/334
• CPC Class Codes: H04L 1/206 for modulated signals
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits

Abstract

A carrier detection circuit for a modem receiver wherein a carrier detect flip-flop is latched upon receipt of initial mark signals of a message. Logic circuits responsive to end-oftransmission signals, noise and signal drop-out control turn-off of the flip-flop. Probability of turn-off due to noise is reduced by delaying turn-off signals due to noise, whereby only a message end code causes rapid turn-off. In addition, a circuit is provided requiring the received signal be in a marking state to enable a fast turn-off.

Claims

1. A modem having a frequency shift keying receiver and a carrier detection circuit, said carrier detection circuit comprising:

a carrier detect latch circuit;

turn-on means for turning said carrier detect latch circuit on in response to mark signals;

first turn-off means for turning said carrier detect latch circuit off in response to an end-of-transmission code;

second turn-off means for turning said carrier detect latch circuit off in response to a long signal drop-out; and

noise turn-off reduction means connected to said first and second turn-off means for preventing transmission line noise from turning off said carrier detect latch circuit.

2. In the carrier detection circuit of claim 1, said carrier detect latch circuit including a flip-flop having an on terminal, an off terminal, and an output terminal.

3. In the carrier detection circuit of claim 1, a signal gate having a first input terminal connected to a frequency shift keying receiver and a second input terminal connected to the output of said carrier detect latch circuit whereby signals are passed by said signal gate only when said carrier detect latch circuit is on.

4. In the carrier detection circuit of claim 1, said turn-on means including;

an envelope detector and low pass filter means responsive to received voice band signals;

a turn-on gate having a first input connected to said low pass filter and a second input responsive to an inverse end-of-transmission signal, whereby said turn-on gate passes a signal turning on said carrier detector latch in response to a received signal.

5. In the carrier detection circuit of claim 4, said first turn-off means including:

a first inverter and a delay integrator connected to the output of said low pass filter;

a second inverter and a first delay line connected to the output of said frequency shift key receiver;

a second delay line connected to the output of said carrier detection latch; and

a first off gate having inputs connected to said delay integrator, to said first delay line and to said second delay line, and an output connected to the off terminal of said carrier detection latch.

6. In the carrier detection circuit of claim 5, said second turn-off means including:

a second off gate including a first input terminal connected to the output of said first inverter, a second input terminal connected to the output of said second delay line, and a third input terminal responsive to the end-of-transmission code, and an output terminal connected in circuit with the off terminal of said carrier detect latch circuit.

7. In a carrier detection circuit for use in connection with a frequency shift keying receiver, the combination of:

a carrier detect latch circuit;

a turn-on gate having a fiRst input responsive to received mark signal levels, a second input responsive to inverted end-of-transmission signals and an output terminal in circuit with said carrier detect latch circuit to turn on said carrier detect latch circuit;

a first turn-off gate having inputs responsive to the inverted, delayed output of said frequency shift keying receiver, to the inverted, integrated mark signal level, and to the carrier detect on signal, and having an output terminal connected to turn off said carrier detect latch circuit;

a second turn-off gate having inputs responsive to the inverted mark signal level, to the carrier detect on signal, and to the end-of-transmission code signal; and

, an output terminal connected to turn off said carrier detect latch circuit.

8. In the carrier detection circuit of claim 7, said carrier detect latch circuit including:

a bi-stable flip-flop circuit having an on terminal, an off terminal, and an output terminal; and

, a gate circuit having a first input connected to the output of said frequency shift keying receiver, a second input connected to said output terminal of said flip-flop circuit, and an output terminal.

9. In the carrier detection circuit of claim 8, said first input of said turn-on gate being connected in circuit with an envelope detector and a low pass filter.

10. In the carrier detection circuit of claim 9, said first turn-off gate including:

a first input in circuit with the output of said frequency shift keying receiver;

a second input in circuit with said first input of said turn on gate, an inverter and a delay integrator;

a third input in circuit with the output of said flip-flop circuit and a delay circuit; and

, an output terminal connected in circuit with the off terminal of said flip-flop circuit.

11. In the carrier detection circuit of claim 10, said second turn-off gate including:

a first input in circuit with the output of said flip-flop circuit and a delay circuit;

a second input in circuit with said first input of said turn-off gate and an inverter;

a third input responsive to an end-of-transmission signal; and

, an output terminal connected in circuit with the off terminal of said flip-flop circuit.