MODEM CARRIER DETECTING CIRCUIT

• US 3,714,586 A
• Filed: 05/18/1971
• Issued: 01/30/1973
• Est. Priority Date: 05/18/1971
• Status: Expired due to Term

• Current Assignee: Edwin E. Mason
• Original Assignee: Edwin E. Mason
• Inventors: Mason, Edwin E.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US05/144,540
• Time in Patent Office: 623 Days
• Field of Search: 178/88 307/231,294 325/319,364,404,409,410,487 329/101,189,192
• US Class Current: 455/337
• CPC Class Codes: H04L 1/206 for modulated signals

Abstract

A modem circuit for distinguishing a frequency shift modulation carrier from noise of a comparable amplitude for use in immediately inhibiting the erroneous response of a data terminal to noise while permitting terminal operation soon after the presence of an acceptable carrier. Noise deadbands are detected and timed and, if 10 milliseconds in duration produce an inhibit output. The inhibit output is maintained for at least 150 milliseconds to permit return of the electromechanical terminal components to a quiescent condition.

Claims

1. A carrier detector circuit for detecting the presence of an acceptable data carrier for controlling a data terminal and comprising:

a. an input circuit means comprising a voltage divider for having the input signal applied thereto, and an input transistor having its input connected to the divider, one output terminal of said input transistor being connected to a source of DC pOwer;

b. a first timing circuit means comprising a first capacitance connected parallel to a first resistance and series connected to a first transistor switch and a source of DC power, the control input terminal of said first transistor switch being connected to the other output terminal of said input transistor;

c. a second timing circuit means comprising a second capacitance connected to a source of DC power and to said other output terminal of said input transistor, said second timing circuit means also having a discharging second transistor switch having its switch terminals connected across said second capacitance, the control input terminal of said second transistor switch being connected between said first capacitance and the first transistor switch of the first timing circuit means and said second timing circuit means also having an output transistor switch having its control input terminal connected at a node between said second capacitance and said input transistor, a switching terminal of said output transistor switch connected to the output terminal of said detector circuit; and

d. a speed up circuit connected to said output transistor switch for speeding its transition from one state to the other, the speed up circuit further comprising;

a first speed up transistor having its switching terminals connected to said source of DC power and to the control input of said output transistor switch for supplying additional turn on current to said output transistor switch shortly after said output transistor switch begins its transition, the speedup transistor having its control input terminal connected to said output terminal of the detector circuit.

2. A circuit according to claim 1 wherein a. a first diode is interposed between the control input terminal of the first speed up transistor and said output terminal in a polarity to permit current flow to said control terminal;

b. a second diode is interposed between said output terminal and said output transistor switch in a polarity to be forward biased when said output transistor is conducting; and

c. a second speed up transistor having its switching terminals connected between said output terminal and a source of DC power and having its control input terminal connected to the output transistor switch side of said second diode.