INSTRUCTION EXECUTION UNIT

• US 3,718,912 A
• Filed: 12/22/1970
• Issued: 02/27/1973
• Est. Priority Date: 12/22/1970
• Status: Expired due to Term

• Current Assignee: Bill C. Madden, Edward H. Sussenguth, John R. Wierzbicki, Leo J. Hasbrouck, Robert P. Rew
• Original Assignee: Bill C. Madden, Edward H. Sussenguth, John R. Wierzbicki, Leo J. Hasbrouck, Robert P. Rew
• Inventors: Hasbrouck, Leo J., Madden, Bill C., Rew, Robert P., Sussenguth, Edward H., Wierzbicki, John R.
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Chirlin, Sydney R.
• Application Number:
  US05/100,704
• Time in Patent Office: 798 Days
• Field of Search: 340/172.5
• US Class Current: 712/217
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

An execution system for instructions having source and sink operand designations includes an arithmetic unit, execution means for holding an instruction for controlling the arithmetic unit and a plurality of operand registers, each having tag means associated therewith for indicating the nature of data stored therein. Instruction modification logic, on the basis of indications of availability of the operand registers, inserts modified source and sink operand register designations in instructions which are then stored in an instruction register stack. Interlock logic controls the transfer of instructions from the instruction register stack to the execution means as a function of the source and sink operand register designations in the modified instructions and the data tags associated with the operand registers.

Claims

1. An instruction execution system comprising an arithmetic unit, execution means for storing an instruction for controlling said arithmetic unit;

further means for storing at least one subsequent instruction;

a plurality of data storage means for use in connection with execution of instructions by said arithmetic unit under the control of an instruction stored in said execution means, means for specifying one of said data storage means for use in connection with the execution of an instruction, storage logic responsive to an instruction for storing an indication of said one of said data storage means specified by said specifying means, and modification logic responsive to said storage logic for inserting in said subsequent instruction the indication of said specified data storage means stored by said storage logic.

2. The system as claimed in claim 1 wherein each said instruction includes a data storage means specifying field and said storage logic includes a plurality of storage means, means responsive to a data storage means specifying field of a first instruction for changing the contents of storage means in said storage logic and means in said modification logic for reading out the contents of storage means in said storage logic as a function of a data storage means specifying field of a subsequent instruction.

3. The system as claimed in claim 1 wherein each said instruction has a plurality of data storage means specifying fields and said storage logic includes means responsive to the contents of first and second data storage means specifying fields of an instruction for changing the contents of storage means in said storage logic and means responsive to a data storage means specifying field of a subsequent instruction for reading out the contents of storage means in said storage logic.

4. The system as claimed in claim 1 and further including data logic for storing indications of validity of data stored in said data storage means.

5. The system as claimed in claim 4 and further including interlock logic responsive to said data logic controlling the transfer of instruction to said execution means.

6. The system as claimed in claim 1 wherein said storage logic includes a plurality of means for storing indications corresponding to specific program named registers.

7. The system as claimed in claim 1 and further including a plurality of instruction storage means for holding instructions waiting transfer to said execution means and interlock logic for controlling the transfer of instructions from said instruction storage means to said execution means.

8. The system as claimed in claim 7 and further including availability logic for providing indications of the data storage means for use in connection with execution of instructions, and means for changing said indications in said availability logic as a function of execution of instructions.

9. The system as claimed in claim 7 wherein said interlock logic includes precedence logic for releasing the oldest non-interlocked instruction in said instruction storage means.

10. The system as claimed in claim 1 wherein said arithmetic unit has a plurality of facilities and further including interlock logic for releasing instructions for transfer to said execution means as a function of the availability of said arithmetic unit facilities.

11. The system as claimed in claim 1 and further including availability logic for providing indications of the data storage means available for use in connection with execution of instructions, and means for changing said indications in said availability logic as a function of execution of instructions.

12. The system as claimed in claim 1 wherein each said instruction has a plurality of data storage means speCifying fields and further including interlock logic for controlling the transfer of instructions to said execution means as a function of the contents of the data storage means specifying fields of successive instructions.

13. The system as claimed in claim 12 and further including data logic for storing indications of validity of data stored in said data storage means.

14. The system as claimed in claim 13 wherein said interlock logic further includes logic responsive to said data logic controlling the transfer of instructions to said execution means.

15. The system as claimed in claim 14 wherein said arithmetic unit has a plurality of facilities and said interlock logic further includes logic for releasing instructions for transfer to said execution means as a function of the availability of said arithmetic unit facilities.

16. The system as claimed in claim 15 wherein said interlock logic further includes precedence logic for releasing the oldest non-interlocked instruction in said instruction storage means for transfer to said execution means.

17. The system as claimed in claim 16 and further including availability logic for providing indications of the data storage means for use in connection with execution of instructions, and means for changing said indications in said availability logic as a function of instruction requests and execution.

18. An execution unit for instructions having sink and source operand designations wherein the source designation specifies the location of an operand and the sink designation specifies a location expected to receive the result of the execution of its instruction comprising an arithmetic unit, execution means for holding an instruction for controlling said arithmetic unit, a plurality of operand registers, each having tag means associated therewith for indicating the nature of the data stored therein, means for inserting identifications of a first particular one of said operand registers to receive a source operand requiring a memory fetch, and a second particular one of said operand registers to receive the result of the execution of an instruction in an instruction to generate a modified instruction, and means for transferring said modified instruction to said execution means for control of said arithmetic unit in the transfer and manipulation of data between the operand registers as specified by said source and sink operand designations in said modified instruction and said arithmetic unit.

19. The unit as claimed in claim 18 and further including availability logic for providing indications of the operand registers available for use in connection with execution of instructions, and means for changing said indications in said availability logic as a function of execution of instructions.

20. The unit as claimed in claim 19 and further including a plurality of instruction registers for holding said modified instructions awaiting transfer to said execution means, and interlock logic for controlling the transfer of instructions from said instruction registers to said execution means.

21. The unit as claimed in claim 20 wherein said arithmetic unit includes add and multiply/divide facilities, and said interlock logic includes sourcesink logic for controlling the transfer of instructions to said execution means as a function of the source and sink operand designations in said modified instructions, operand validity logic for controlling the transfer of instructions to said execution means as a function of said tag means, facility available logic for controlling the transfer of instructions to said execution means as a function of the availability of the arithmetic unit facilities, and precedence logic for controlling the transfer of the oldest non-interlocked instruction in said instruction registers to said execution means.

22. The unit as claimed in claim 18 wherein said identification inserting means includes means for storing the identifications of a plurality of said Operand registers, means responsive to a first instruction for changing the identity of an operand register stored in said identification inserting means, means responsive to a second instruction for modifying an instruction to insert an operand register identity stored in said identification inserting means and the identity of a second operand register in said second instruction and means responsive to a third instruction for inserting two operand register identities stored in said identification inserting means in said third instruction.

23. The unit as claimed in claim 22 and further including availability logic including means for providing indications of the operand registers available for use in connection with the execution of instructions, and means for changing said availability indications as a function of instruction requests and instruction execution, and wherein the second operand register identification is inserted in said first instruction in response to said operand register availability indications provided by said availability logic and said changing means changes the availability indication of the operand register identified by said second operand register identification in said second instruction in response to a signal from said execution means when said second instruction is in said execution means.