DIGITAL LINEARIZER AND METHOD

• US 3,719,807 A
• Filed: 04/15/1970
• Issued: 03/06/1973
• Est. Priority Date: 04/15/1970
• Status: Expired due to Term

• Current Assignee: EOG, Inc. (Sanmina-SCI Corporation)
• Original Assignee: Francis Darnall Jr. Daley
• Inventors: Daley, Francis Darnall Jr.
• Primary Examiner(s): Cook, Daryl W.
• Assistant Examiner(s): Thesz, Joseph M.
• Application Number:
  US05/028,646
• Time in Patent Office: 1,056 Days
• Field of Search: 235/92PE,92PL,154 340/347AD
• US Class Current: 377/50
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/48 Servo-type converters

Abstract

A digital linearizer is provided, having a binary coded digital counter and a primary bit generating means for generating a bit count which is a direct function of a a non-linearly measured variable desired to be linearly digitally indicated by the counter. The primary bit input into the counter is controlled by a gate arrangement which enables the addition of a next succeeding accumulative bit from the primary bit source, the addition of a supplementary bit to the counter between primary bit additions, or the inhibiting or defeating of the entry of a bit from the primary bit source to the counter. This gate arrangement is in turn controlled as a function of the examination of each individual sequential numerical count in the counter, and at selected predetermined individual numerical count values in the counter a supplementary compensating bit is added through the gate to the counter, or is effectively subtracted by inhibiting a next succeeding primary bit, based upon a predetermined calculation of theretofore non-compensated nonlinearity error required to be compensated at the individual count value in the counter.

Claims

1. A digital linearizer for non-linearly appearing variables desired to be digitally indicated or recorded in linearized form, comprising a digital counter a base pulse generator for generating a quantum pulse count in the form of a train of pulses varying in total quantity as a predetermined function of a non-linear variable to be indicated or recorded, connecting means connecting the output of said base pulse generating means to said counter, supplementary count adding means having an output in individual count adding connection to said digital counter, selective individual-discrete-count-responsive add gate means connected in responsive relation to the count output of said counter and being connected in count output responsive controlling relation to said supplementary count adding means, count defeat means operative to defeat the change of count state of said counter by a pulse from said base pulse generating means, and selective individual-discrete-count-responsive subtract gate means connected in responsive relation to the count output of said counter and being connected in count output responsive controlling relation to said count defeat means.

2. A digital linearizer according to claim 1, further comprising gate-control means for selectively modifying said individual-discrete-count-responsive add gate means and subtract gate means to enable linearizing accommodation of different non-linear variables desired to be linearized.

3. A digital linearizer according to claim 2, said count adding means comprising a gate in controlling relation to said counter, and an add pulse generator having its output connected in controlling relation to said counter, said add pulse generator being disabled except in the presence of an add command from said add gate means.

4. A digital linearizer according to claim 3, said count adding means further comprising time delay pulse generating means responsive to the output from said base pulse generator and having its output effectively connected in controlling relation to said add pulse generator to effect generation of an add pulse by said add pulse generator in the presence of an add command from said add gate means and after completion of the registry of a first base pulse count by said counter and before the registry of a succeeding base pulse count by said counter.

5. A digital linearizer according to claim 4, further comprising second time delay pulse generating means and a second add pulse generator, said second add pulse generator having its output connected in controlling relation to said counter, said second add pulse generator being disabled except in the presence of an add command from said add gate means, said second time delay pulse generating means being responsive to the output from said base pulse generator and having its output effectively connected in controlling relation to said add pulse generator to effect generation of an add pulse by said add pulse generator in the presence of an add command from said add gate means and after completion of the registry of a first base pulse count by said counter and before the registry of a succeeding base pulse count by said counter, said second time delay pulse generating means having a longer time delay period than the first said time delay pulse generating means to enable the generation of a second add pulse after said add pulse from said first add pulse generator, and further selective individual-discrete-count-responsive add gate means connected in add command cOntrolling enabling relation to said second add pulse generator.

6. A digital linearizer according to claim 1, said count adding means comprising a gate in controlling relation to said counter, and an add pulse generator having its output connected in controlling relation to said counter, said add pulse generator being disabled except in the presence of an add command from said add gate means.

7. A digital linearizer according to claim 6, said count adding means further comprising time delay pulse generating means responsive to the output from said base pulse generator and having its output effectively connected in controlling relation to said add pulse generator to effect generation of an add pulse by said add pulse generator in the presence of an add command from said add gate means and after completion of the registry of a first base pulse count by said counter and before the registry of a succeeding base pulse count by said counter.

8. A digital linearizer according to claim 7, second time delay pulse generating means and a second add pulse generator, said second add pulse generator having its output connected in controlling relation to said counter, said second add pulse generator being disabled except in the presence of an add command from said add gate means, said second time delay pulse generating means being responsive to the output from said base pulse generator and having its output effectively connected in controlling relation to said add pulse generator to effect generation of an add pulse by said add pulse generator in the presence of an add command from said add gate means and after completion of the registry of a first base pulse count by said counter and before the registry of a succeeding base pulse count by said counter, said second time delay pulse generating means having a longer time delay period than the first said time delay pulse generating means to enable the generation of a second add pulse after said add pulse from said first add pulse generator, and further selective individual-discrete-count-responsive add gate means connected in add command controlling enabling relation to said second add pulse generator.

9. A digital linearizer according to claim 1, said count defeat means comprising a first bi-stable switch having an output in controlling relation with the input to said counter from said count adding means, and being responsive to a time sequence combination of a signal from said subtract gate means and the occurrence of a base pulse by said base pulse generating means.

10. A digital linearizer according to claim 9, further comprising further pulse generating means operative to generate a pulse of longer duration than the duration of each of said base pulses, but of shorter time duration than the time period between succeeding said base pulses, said bi-stable switch being responsive to the output of said further pulse generating means to switch between its bi-stable conditions.

11. A digital linearizer according to claim 10, further comprising enabling means enabling switching of said bi-stable switch in response to successive pulses from said further pulse generator only when a subtract command is in existence as a function of said subtract gate means.

12. A digital linearizer according to claim 11, said enabling means comprising further gate means between said subtract gate means and said bi-stable switch, and having one of its inputs responsive to the output from said subtract gate means, and a further bi-stable switch in feed-back relation with another input to said further gate means, and having a control input thereto connected to the output of said further gate means.

13. A digital linearizer according to claim 12, further comprising gate-control means for selectively modifying said individual-discrete-count-responsive gate means to enable linearizing accommodation of different non-linear variables desired to be linearized.

14. A digitAl linearizer according to claim 9, further comprising gate-control means for selectively modifying said individual-discrete-count-responsive add gate means and subtract gate means to enable linearizing accommodation of different non-linear variables desired to be linearized.

15. A digital linearizer according to claim 1, said counter being a binary coded decimal accumulator, and having visual readout means associated therewith.

16. A digital linearizer according to claim 1, said individual-discrete-count-responsive gate means comprising a plurality of discrete count gates each having an input from said counter corresponding to a unique discrete unitary count value, a first plurality of said discrete count gates being connected in said controlling relation to said count adding means, and a second plurality of said discrete count gates being connected in said controlling relation to said count defeat means.

17. A digital linearizer for linearizing non-linear variables, comprising an analog-to-frequency converter having an analog input and a variable frequency output as a function of the quantum value of the analog input thereto, a time interval controlled gate for selectively passing a cyclic signal which has cyclic variations as a function of the variable frequency output of said analog-to-frequency converter during a predetermined time interval, a readout count accumulator having a count adding input for adding counts thereto as a function of succeeding cycles of said cyclic signal during a said predetermined time interval, gate matrix means connected in controlled relation to an output of said readout count accumulator, and having discrete count value gates corresponding to individual ones of selected numerical count locations in said accumulator, a common count corrective unit in controlling relation with said count adding input to said readout count accumulator, and selective connecting means for selectively connecting said discrete count value gates in controlling relation to said common count corrective unit.

18. A digital linearizer according to claim 17, further comprising means for connecting a plurality of said accumulator count value gates in controlling relation to said common count corrective unit.

19. A digital linearizer according to claim 18, further comprising a second common count corrective unit in controlling relation with the connection to said readout, and means for connecting a different plurality of said accumulator count gates in controlling relation to said second common count corrective unit.

20. A digital linearizer according to claim 19, one of said common count corrective units being a positive add count unit, and the other of said common count corrective units being a defeat count unit operative to defeat the normal addition of a next succeeding time interval count in said accumulator as a function of the output of said converter.

21. A digital linearizer for non-linearly appearing variables desired to be digitally indicated or recorded in linearized form, comprising a digital counter base primary bit supplying means for supplying a quantum bit count varying in quantity proportional to the value of a non-linear variable to be recorded or indicated, connecting means connecting the output of said primary bit supplying means to said counter, count adding means having an output in individual bit count adding connection to said digital counter, selective individual-discrete-selective count-responsive add gate means connected to the count output of said counter and being connected in controlling relation to said count adding means, count defeat means operative to defeat the change of bit count state by said counter by a pulse from said primary bit supplying means, and selective individual-discrete-count-responsive subtract gate means connected to the count output of said counter and being connected in controlling relAtion to said count defeat means.

22. A digital linearizer according to claim 21, further comprising gate-control means for selectively modifying said individual-discrete-count-responsive add gate means and subtract gate means to enable linearizing accommodation of different non-linear variables desired to be linearized.

23. A digital linearizer according to claim 21, said count adding means comprising a gate in controlling relation to said counter, and an add bit generator having its output connected in controlling relation to said counter, said add bit generator being disabled except in the presence of an add command from said add gate means.

24. A digital linearizer according to claim 21, said count defeat means comprising a first bi-stable switch having an output in controlling relation with the input to said counter from said count adding means, and being responsive to a time sequence combination of a signal from said subtract gate means and the occurrence of a primary bit by said primary bit supplying means.