PROGRAMMABLE TIMER FOR CONTROLLING THE INJECTION OF ADDITIVES TO A DRY CLEANING SOLVENT CHARGE

• US 3,721,908 A
• Filed: 08/25/1971
• Issued: 03/20/1973
• Est. Priority Date: 08/25/1971
• Status: Expired due to Term

• Current Assignee: Ojars Jurjans
• Original Assignee: Ojars Jurjans
• Inventors: Jurjans, Ojars
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/174,627
• Time in Patent Office: 573 Days
• Field of Search: 307/293 317/141S 307/132E,132EA 328/129-131,48,49,63,72-75 235/151.12
• US Class Current: 327/392
• CPC Class Codes: G05B 19/102 for input of programme steps, i.e. setting up sequence

Abstract

A programmable timer for controlling the proportional and volumetric addition of additives to a dry cleaning solvent charge, utilizes an oscillator, binary counter frequency dividers, and a four line to 16 line decoder to establish selective time reference intervals. Material feed control solenoid valves are controlled by flip-flop circuits. Materials feed is initiated by causing the flip-flip circuits to assume one stable state to energize the solenoid valves, and material feed is terminated by the decoder outputs, indicative of selected time intervals, causing the flip-flop circuits to assume the other stable state to deenergize the solenoid valves.

Claims

1. A chemical processing program control circuit, comprising timer means for applying a signal to a plurality of terminals in a predetermined time sequence, a plurality of bistable means each having first and second stable states, feed control means coupled to each of said bistable meanS for activation when its respective bistable means is in said first stable state and deactivation when its respective bistable means is in said second stable state, means for placing said bistable means in said first stable state, means coupling selected ones of said terminals to selected ones of said bistable means to place each of said bistable means in said second stable state when said signal is applied to said terminal coupled thereto, and means coupling said bistable means to said timer means for activating said timer means while at least one of said bistable means is in said first stable state and for deactivating said timer means when none of said bistable means is in said first stable state.

2. A circuit as set forth in claim 1, wherein said plurality of bistable means are flip-flop circuits.

3. A circuit as set forth in claim 2, wherein said feed control means comprise a series of solenoid valves.

4. A circuit as set forth in claim 3, wherein said feed control means further comprise amplifiers in series with said solenoid valves and coupled to respective flip-flop circuits for said activation and deactivation of the feed control means.

5. A circuit as set forth in claim 4, wherein the coupling between at least one of said flip-flop circuits and its respective amplifier is through an AND gate, and said circuit further includes means coupling a cyclic signal from said timer means to said AND gate to cause said amplifier to by cycled on and off during the period that said one flip-flop is in said first stable state.

6. A circuit as set forth in claim 2, wherein said means coupling said bistable means to said timer is an OR gate.

7. A chemical processing program control circuit, comprising timer means for applying a signal to a plurality of terminals in a predetermined time sequence, a bistable means having first and second stable states, feed control means coupled to said bistable means for activation when said bistable means is in said first stable state and deactivation when said bistable means is in said second stable state, means for placing said bistable means in said first stable state, selector means coupling a selected one of said terminals to said bistable means to place said bistable means in said second stable state when said signal is applied to said terminal coupled thereto, said feed control means comprising a control amplifier coupled to said bistable means to be activated and deactivated respectively by said first and second stable states of said bistable means, the coupling between said bistable means and said amplifier being through an AND gate, and said circuit further including means coupling a cyclic signal from said timer means to said AND gate to cause said amplifier to be cycled on and off during the period that said bistable means is in said first stable state.