TEMPERATURE CONTROLLED CLOCKING OF LOGIC CIRCUITS

• US 3,725,789 A
• Filed: 12/21/1970
• Issued: 04/03/1973
• Est. Priority Date: 12/21/1970
• Status: Expired due to Term

• Current Assignee: Donald V. Mager
• Original Assignee: Donald V. Mager
• Inventors: Mager, Donald V.
• Primary Examiner(s): Saalbach, Herman Karl
• Assistant Examiner(s): Davis, B. P.
• Application Number:
  US05/099,879
• Time in Patent Office: 834 Days
• Field of Search: 331/66,70 307/310
• US Class Current: 307/651
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03L 1/026 by using a memory for digitally storing correction values H03L1/025 takes precedence

Abstract

A variable frequency pulse generator whose pulse repetition rate is controlled as a function of temperature is used as a source of gating signals for a logic array so that the propagation delay of data signals through the logic array is optimized.

Claims

1. In a digital logic circuit array of the type wherein digital data signals are propagated therethrough in synchronism with timed gating signals having a variable pulse repetition rate, the combination comprising:

a variable frequency pulse generator for generating timed gating signals having a variable pulse repetition rate;

a source of digital data signals;

a digital logic circuit adapted to receive said digital data signals from said source of digital data signals and to receive said gating signals from said pulse generator; and

, temperature responsive means operatively connected to said pulse generator and controlling the pulse repetition rate of said pulse generator for gating said digital data signals through said logic circuit at a pulse repetition rate that is a function of ambient temperature.

2. A method for operating a semiconductor logic circuit array of the type wherein digital data signals are allowed to propagate through the array in synchronism with sequentially applied timing pulses comprising the steps of:

generating a series of timing pulses;

applying said timing pulses to an array of semiconductor logic circuits;

generating digital data signals;

applying said digital data signals to said array of logic circuits;

varying the propagation delay time of said digital data signals through said array of logic circuits as a function of the temperature variation thereof;

sensing the temperature of said array of logic circuits;

varying the rate at which said timing pulses are generated as a function of the temperature of said array of logic circuits;

synchronizing the variation of the rate at which said timing pulses are generated with the variation of said propagation delay time.

3. The combination comprising:

a variable frequency pulse generator for generating gating pulses having a variable pulse repetition rate;

a digital logic circuit having a variable propagation delay of digital data signals propagated therethrough which delay is temperature dependent;

a source of digital data signals coupled to said digital logic circuit for propagating said digital data signals therethrough;

means coupling said gating pulses to said digital logic circuit; and

, temperature responsive means coupled to said pulse generator for varying said pulse repetition rate in synchronism with the variable propagation delay of sAid digital data signals through said digital logic circuit.

4. The method of optimizing the propagation rate of digital data signals through a digital logic circuit having a temperature dependent propagation delay, comprising:

generating a series of gating pulses;

coupling a digital data signal to a digital logic circuit that has a variable propagation delay of said digital data signal therethrough that is temperature dependent;

coupling said gating pulses to said digital logic circuit;

sensing the change of temperature of said digital logic circuit;

varying the pulse repetition rate of said gating pulses in response to said change of temperature; and

, synchronizing said pulse repetition rate variation with said propagation delay variation.