SMALL RECONFIGURABLE PROCESSOR FOR A VARIETY OF DATA PROCESSING APPLICATIONS

• US 3,725,868 A
• Filed: 10/19/1970
• Issued: 04/03/1973
• Est. Priority Date: 10/19/1970
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Cornelius C. Perkins, Donald W. Waldenmayer, Leonard R. Gardner, Michael M. Malmer Jr, Patrick J. Chowning
• Inventors: Malmer, Michael M. Jr., Perkins, Cornelius C., Waldenmayer, Donald W., Chowning, Patrick J., Gardner, Leonard R.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/081,786
• Time in Patent Office: 897 Days
• Field of Search: 340/172.5
• US Class Current: 712/245
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 9/262 Arrangements for next microinstruction selection

Abstract

An improved microinstruction data processor capable of operating as an independent processor or as a terminal unit for a large general purpose computer employing a read/write disk memory to hold both macroinstructions and microinstructions, wherein the microinstructions implement macroinstructions. The memory has a macroinstruction portion and a microinstruction portion having a changeable boundary therebetween to accomodate a variable number of microinstructions. A push-down stack facilitates microprogram branching and returning by holding microinstruction return addresses when microinstructions call for branching to microprogram subroutines. A microinstruction decoding register augmented with a microinstruction buffer register decodes a previously fetched microinstruction while a new microinstruction is fetched from memory.

Claims

1. An improved serial operation microprogram reconfigurable data processor wherein macroinstructions are implemented directly by microinstructions comprising:

a disk memory for storing both macroinstructions and microinstructions input into said processor;

program control means connected to said disk memory including;

means for loading both macroinstructions and microinstructions into seperable portions of said memory in sequential strings of operation and whereby a dynamic boundary is established between said two types of instructions stored, means associated with said loading means for reading said stored macroinstructions and said stored microinstructions in the sequential order of operation in which they are stored, said reading means including means for fetching one of said microinstructions from said disk memory while decoding a previously fetched microinstruction, means associated with said reading means for implementing by microinstructions macroinstructions which have been read, data manipulation means connected to said disk memory for the manipulation of data according to macroinstructions stored in said disk memory as implemented by microinstructions stored in said disk memory; and

said implementing means including means for branching to read other strings of microinstructions, including storage means for storing branch return addresses in a first in last out manner.

2. The apparatus of claim 1 wherein said program control loading means includes:

a single base register;

means for loading information into said base register for establishing the boundary between said macroinstruction portion and said microinstruction portion of said disk memory; and

means associated with said base register loading means responsive to microinstruction storage requirements for automatically changing said base register boundary as said microinstruction storage requirements change.

3. The apparatus of claim 2 wherein said program control loading means also includes:

means associated with said base register for assigning positive address values to macroinstructions and negative address values to microinstructions respectively;

means associated with said assigning means for adding said assigned respective address values to the established boundary in said base register; and

means associated with said adding means for designating each summation as the storage address of the respective macroinstruction or microinstruction.