POST STORAGE RANGE AND DOPPLER CORRELATION METHOD AND APPARATUS

• US 3,725,916 A
• Filed: 09/01/1967
• Issued: 04/03/1973
• Est. Priority Date: 09/01/1967
• Status: Expired due to Term

• Current Assignee: Thomas P. Cutler
• Original Assignee: Thomas P. Cutler
• Inventors: Cutler, Thomas P.
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US04/665,069
• Time in Patent Office: 2,041 Days
• Field of Search: 343/5DP,17.2DC,100.7,17.1 235/150.53,181
• US Class Current: 342/110
• CPC Class Codes: G01S 13/28 with time compression of received pulses
• CPC Class Codes: G01S 13/288 phase modulated
• CPC Class Codes: G01S 13/64 Velocity measuring systems using range gates

Abstract

Apparatus is herein disclosed for processing signals by storing and correlating with preset programs. The apparatus is disclosed as it relates to a pulse doppler radar application. Target reflected coded signals modulated by doppler are partly correlated to resolve ranges which are ambiguous with relation to the remaining uncorrelated code. The partly correlated signal is stored in a magnetic core matrix. A series of stitching networks wired (or stitched) in accordance with predetermined range and doppler combinations are coupled to the storage matrix so that when the signals stored in the matrix are read out to the stitch networks, correlation of the remaining ambiguity will occur indicating unambiguous range and doppler of targets. The stitch networks compare the stored code time histories with the preset codes representing a combined range and doppler signal.

Claims

1. A signal processor for processing signals made up of more than one code, comprising:

input means;

means coupled to said input means for partly correlating the signals to correlate all but one code;

means for storing said partly correlated signals; and

a sigNal correlation network coupled to said storage means for correlating said partly correlated signals.

2. A signal processor as defined in claim 1, in which said partial correlation means includes:

a passive network of a first plurality of series connected delay lines equal to the number of bits in the code to be removed less one;

a plurality of inverters coupled to selected ones of said delay lines and/or input means;

a second plurality of series connected delay lines equal to the number of bits of the code to be removed less one, coupled to said input means, to said inverters and to the non-selected first series of delay lines;

a plurality of gates equal to the number of bits in the code to be removed, one each of said gates being coupled to said input means and to said second plurality of delay lines; and

means for opening said gates for a preselected time period.

3. A signal processor as defined in claim 2, in which said first and second plurality of delay lines are each of a duration corresponding to the time between successive pulses of the code to be correlated.

4. A signal processor as defined in claim 2, in which said selected ones of said delay lines and/or input means correspond to opposite sense bits of the code to be correlated.

5. A signal processor as defined in claim 2, in which said preselected time period is equal to the pulse width of a pulse in said code to be correlated.

6. A signal processor as defined in claim 1, in which said correlation means includes:

a shift register;

a clock coupled to the input to said shift register; and

a plurality of groups of phase inversion switches, each group coupled to a selected tap of said shift register, with outputs from said phase inversion switches being coupled to said storage means.

7. A signal processor as defined in claim 6, in which said shift register has a plurality of taps equal to the number of bits of the code to be correlated.

8. A signal processor as defined in claim 1, in which said means for storing said partly correlated signals includes:

an orthogonal storage matrix comprising a multiplicity of bi-stable logic elements arranged in rows and columns, an electrical conductor connected to the bi-stable logic elements of each row of bi-stable logic elements, an electrical conductor connected to the bi-stable logic elements of each column of bi-stable logic elements; and

means for applying said partly correlated signals to said orthogonal storage matrix.

9. A signal processor as defined in claim 8, in which said means for applying said partly correlated signals to said orthogonal storage matrix includes means for sequentially applying write pulses to the conductors connecting said columns of bi-stable logic elements simultaneously with the application of said partly correlated signals to the conductors connecting said rows of bi-stable logic elements, said write pulses being applied at the rate at which said one code was generated.

10. A signal processor as defined in claim 9, in which said bi-stable logic elements are magnetic cores.

11. A signal processor as defined in claim 1, in which said signal correlation network includes a multiplicity of networks of multi-level elements each network of elements grouped to sum substantially all of a multiplicity of simultaneously presented pulses representing the polarity characteristics as a function of time of a particular signal only.

12. A signal processor as defined in claim 11, in which said multi-level elements are toroids having linear transformer magnetic characteristics.

13. In a pulse doppler radar system in which the transmitted signal is comprised of a first code modulated by at least one other code, each code representing different size range intervals, a receiver signal processor, comprising:

input means;

means coupled to said input means for partly correlating received target reflected signals to remove all but one code, thus acquiring fine range reSolution in one broad ambiguous range interval;

means for storing said partly correlated signals; and

a signal correlation network coupled to said storage means for correlating said partly correlated signals.

14. A signal processor as defined in claim 13, in which said partial correlating means includes a network comprising:

a first plurality of series connected delay lines equal to the number of bits in said first code less one;

a plurality of inverters coupled to selected ones of said delay lines and/or input means which correspond to opposite sense bits of said first code;

a second plurality of series connected delay lines equal to the number of bits of said first code less one, coupled to said input means, to said inverters and to the non-selected first plurality of delay lines;

a plurality of gates equal to the number of bits in said first code, one each of said gates being coupled to said input means and to said second plurality of delay lines; and

means for opening said gates for a period of time equal to the width of one of said first code bits.

15. A signal processor as defined in claim 14, in which said partial correlation means includes additional networks, one for each code in the transmitted signal less two.

16. A signal processor as defined in claim 13, wherein said partly correlated signals represent range resolved in a single ambiguous range interval modulated by doppler and in which said storing means includes:

an orthogonal storage matrix comprising a multiplicity of bi-stable logic elements arranged in rows and columns, an electrical conductor connected to the bi-stable logic elements of each row of bi-stable logic elements, an electrical conductor connected to the bi-stable logic elements of each column of bi-stable logic elements; and

means for applying said partly correlated signals to said orthogonal storage matrix.

17. A signal processor as defined in claim 13, in which said signal correlation network includes a multiplicity of networks of multi-level elements, each network of elements grouped to sum substantially all of a multiplicity of simultaneously presented pulses representing the polarity characteristics as a function of time of a particular signal only.

18. A signal processor as defined in claim 13, in which signal correlation network includes a plurality of stitching networks of multi-level elements so stitched as to respond to only a particular range-doppler combination.

19. A signal processor as defined in claim 18, in which said multi-level elements are toroids having linear transformer magnetic characteristics.

20. A method for resolving range and doppler of received target signals after transmitting a signal comprising a first code modulated by one or more codes, comprising the steps of:

partly correlating the received signals to remove all but one code;

storing the partly correlated signals; and

correlating the stored signals with predetermined programs representing various range and doppler combinations.