LINE AND LINK SENSING TECHNIQUE FOR PABX TELEPHONE SYSTEM

• US 3,729,594 A
• Filed: 07/22/1971
• Issued: 04/24/1973
• Est. Priority Date: 07/22/1971
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: Charles J. Simon, Elmer W. Krock
• Inventors: Krock, Elmer W., Simon, Charles J.
• Primary Examiner(s): Cooper, William C.
• Application Number:
  US05/165,259
• Time in Patent Office: 642 Days
• Field of Search: 179/18AB,18ES
• US Class Current: 379/270
• CPC Class Codes: H04Q 3/545 using a stored programme

Abstract

A technique for detecting the busy or idle status of lines, links and peripheral equipment in an electronic private branch telephone system. Each crosspoint in the system includes an extra contact over which a sensing path is established. Ring cores provide an indication of a completed path which is noted by the telephone system'"'"''"'"'s common control equipment.

Claims

1. A communication system including:

a plurality of peripheral circuits including a plurality of lines, a plurality of trunks, and a plurality of registers;

a switching network for interconnecting said peripheral circuits;

marker means connected to said switching network;

a central processor operated to control said marker means to operate said switching network to selectively interconnect said peripheral circuits;

scanning means under control of said central processor operated to periodically determine the busy/idle status of said switching network;

said switching network comprising, a plurality of matrices each including a plurality of crosspoints operable in response to said marker, to establish circuit connections through said switching network between said peripheral circuits, a portion of said crosspoints each including associated means for indicating the operational state of said associated crosspoint;

said scanning means periodically operated under control of said central processor to scan said indicating means to determine the operational state of said associated crosspoints, whereby the operated status of connecting paths through said associated crosspoints is determined, permitting said central processor to select connecting paths through said switching network between said peripheral circuits.

2. A communication system as claimed in claim 1 wherein said plurality of matrices include:

a first matrix comprising a first stage including a plurality of crosspoints having circuit connections to a portion of said peripheral circuits, and a second stage including a plurality of crosspoints having circuit connections to said first stage crosspoints, a plurality of indicating means each associated with a different one of said second stage crosspoints; and

a second matrix comprising a first stage including a plurality of crosspoints having circuit connections to said first matrix second stage crosspoints and a plurality of circuit connections to a portion of said peripheral circuits, a last stage including a plurality of cross points having circuit connections to said first matrix second stage crosspoints and to a portion of said plurality of peripheral circuits, and an intermediate stage interconnecting said first and last stage crosspoints said intermediate stage including a plurality of crosspoints and a plurality of indicating means each associated with a different one of said intermediate stage crosspoints.

3. A communication switching system as claimed in claim 2 wherein:

said scanning means under control of said central processor are oPerated periodically to determine the busy/idle status of circuit connections from selected ones of said peripheral circuits to said first matrix stage, and through said first matrix second stage to said second matrix, by interrogation of selected ones of said indicating means associated with the crosspoints of said first matrix second stage.

4. A communication switching system as claimed in claim 2 wherein:

said scanning means under control of said central processor are operated periodically to determine the busy/idle status of selected circuit connections through said second matrix from circuits connected to said second matrix first stage, to circuit connections to said second matrix last stage, through said intermediate stage interconnections between said first and last stages by interrogation of selected ones of the indicating means associated with the crosspoints of said second matrix intermediate stage.

5. A communication switching system as claimed in claim 2 wherein:

periodic operation of said scanning means under control of said processor to periodically interrogate said indicating means associated with said first matrix second stage and said second matrix intermediate stage are effective to indicate to said central processor the busy/idle status of interconnecting paths through said switching network, whereby interconnection paths for said peripheral circuits are determined.

6. A communication system as claimed in claim 2 wherein:

said indicating means included in said first matrix and in said second matrix each comprise a plurality of pairs of switching contacts operable in response to operation of said associated crosspoints, said contacts arranged in matrix form comprising a plurality of rows and a plurality of columns, the first contact of each pair of said switching contact pairs in each of said rows connected to a circuit bus common to each row and the second contact of each pair of said switching contact pairs in each of said columns connected to a circuit bus common to each column.

7. Switching means as claimed in claim 6 wherein:

each of said common busses associated with each row of contacts is connected at one end to a first common pulse source and connected at the other end to circuit completion means individual to said bus;

readout means connected between said first common pulse source and said busses associated with each of said rows;

said readout means further including circuit connections to said central processor;

said first common pulse source and a selected one of said first individual circuit completion means periodically operated by said scanning means;

operation of any of said switching contacts in said row effective in combination with operation of said first common pulse source and said selected first individual circuit completion means, to cause operation of said readout means to provide an indication to said central processor of the busy status of at least one of the crosspoints associated with switching contacts of said row.

8. Switching means as claimed in claim 7 wherein:

each of said common busses associated with each column of contacts is connected at one end to a second common pulse source and connected at the other end to second circuit completion means individual to said bus;

readout means connected between said second common pulse source and said busses associated with each column;

said readout means further including circuit connections to said central processor;

said second common pulse source and a selected one of said second individual circuit completion means periodically operated by said scanning means;

operation of any of said switching contacts in combination with operation of said second common pulse source and a selected one of said individual circuit effective to cause operation of said readout means to provide an indication of said central processor of the busy status of at least one of the crosspoints associated with the switching contacts of said column.

9. Switching means as claimed in claim 8 wherein:

peRiodic selective operation by said central processor said first and second common pulse sources and said first and second circuit completion means in combination with operation of any of said switching contacts in said matrices are effective to cause operation of said readout means to provide an indication to said central processor of the busy status of selected crosspoints included in said matrix.