ERROR DETECTING AND CORRECTING APPARATUS FOR USE IN A SYSTEM WHEREIN PHASE ENCODED BINARY INFORMATION IS RECORDED ON A PLURAL TRACK

• US 3,729,708 A
• Filed: 10/27/1971
• Issued: 04/24/1973
• Est. Priority Date: 10/27/1971
• Status: Expired due to Term

• Current Assignee: Allan J. Wolfer, Edward Cooper
• Original Assignee: Allan J. Wolfer, Edward Cooper
• Inventors: Wolfer, Allan J., Cooper, Edward
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/192,865
• Time in Patent Office: 545 Days
• Field of Search: 340/146.1,146.1AG,146.1F,174.1B
• US Class Current: 714/746
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs

Abstract

In apparatus for decoding a byte of phase encoded binary information having a plurality of information bits and one parity check bit for the information bits and wherein each such bit is recorded in a selected one of a plurality of tracks on a suitable information storage medium such as a magnetic tape, circuit means is provided for detecting parity errors in the information bits of each byte and for correcting a single missing information bit. Further, if more than one bit within a single byte of information is missing, the circuit means provide at the output a signal or manifestation indicative of such multiple error.

Claims

1. In apparatus for decoding and processing bytes having a plurality of information bits and one parity check bit for the information bits respectively, with the bits of such bytes being recorded in a phase encoded format in selected ones of a plurality of tracks on an information storage medium respectively, the improvement comprising:

a. signal conditioning circuit means adapted to be coupled to the tracks for deriving electrical signals corresponding to the bits of a byte, said signal conditioning circuit means including;

i. error detection means associated with the tracks and responsive to the failure to decode an information bit for providing an error signal indicative thereof, and b. output logic means including;

i. parity check means;

ii. correction means coupled to said error detection means and said parity check means and responsive to a single error signal for correcting the error condition by inserting a signal bit in the electrical signals associated with such single error signal which satisfies parity check;

iii. means for applying the corrected electrical signals corresponding to the information bits recorded upon the plurality of tracks to a set of corresponding output terminals; and

iv. blocking means coupled to said error detection means and responsive to error signals indicative of error conditions in more than one information bit for providing a manifestation that the decoded byte has an error.

2. The invention as set forth in claim 1 wHerein there is recorded in the tracks start of data manifestations indicating the beginning of the bytes having information bits, and including second error detection means associated with the tracks and responsive to the failure to decode a start of a data manifestation in a track for producing a second signal;

and said blocking means being responsive to two or more first and/or second signals for providing a manifestation that the decoded byte has an error.