POLYPHASE ENCODING-DECODING SYSTEM

• US 3,731,311 A
• Filed: 09/18/1970
• Issued: 05/01/1973
• Est. Priority Date: 09/18/1970
• Status: Expired due to Term

• Current Assignee: Frederick C. Williams
• Original Assignee: Frederick C. Williams
• Inventors: Williams, Frederick C.
• Primary Examiner(s): Bentley, Stephen C.
• Application Number:
  US05/073,470
• Time in Patent Office: 956 Days
• Field of Search: 235/181 343/17.2R,17.2PC,5DP,1CL
• US Class Current: 342/201
• CPC Class Codes: G01S 13/28 with time compression of received pulses
• CPC Class Codes: G01S 13/288 phase modulated
• CPC Class Codes: H04L 27/2332 using a non-coherent carrier
• CPC Class Codes: H04L 27/2337 using digital techniques to measure the time between zero-crossings

Abstract

A polyphase pulse compression system for simultaneously decoding and amplitude weighting groups of sequentially applied phase encoded signals. For a phase encoded signal group of N2 signal elements the decoded amplitude weighted value of a particular signal group is formed by modifying only N stored subaccumulation signals from the preceding decoding cycle. Dual processing storage channels associated with each sub-accumulation signal are alternately cleared to reduce processor error '"'"''"'"''"'"''"'"'buildup.

Claims

1. A device for consecutively decoding and amplitude weighting groups of sequentially applied phase encoded signals, said device comprising:

a memory device having an input circuit for receiving said applied phase encoded signals and having a plurality of output circuits;

a plurality of processing subsections with each subsection including accumulator means for providing during each one of a plurality of processing cycles a sub-accumulation signal that approximates the amplitude weighted phase decoded value of one subsequence of said applied phase encoded signals, means for storing said sub-accumulation signal, multiplier means coupled between the output of said means for storing and one input of said accumulator means for multiplying said stored subaccumulation signal by a fixed predetermined value, and coupling means for coupling the output of said accumulator means to the input of said means for storing; and

signal modifying means coupled between said plurality of output circuits of said memory device and other inputs of said accumulator means of each said subsection for modifying the value of said applied encoded signals and for applying said modified signals to said accumulator means;

whereby the stored sub-accumulation signals are modified as a function of the amplitude weighted differences between the signal group associated with said stored sub-accumulation signals and the next signal group, to form a new set of subaccumulation signals associated with said next signal group.

2. The device of claim 1 wherein said signal modifying means included a plurality of multiplier units, each coupled to a different one of said plurality of memory device output circuits for modifying the associated signal applied from said memory device as a function of a preselected fixed amplitude weighting value.

3. The device of claim 2 wherein each said accumulator means includes means for adding one of said modified signals to and subtracting another of said modified signals from said stored sub-accumulation signal forMed during the last preceding processing cycle.

4. The device of claim 3 wherein said multiplier means includes means for multiplying said stored sub-accumulation signal by a function of the encoded phase of the associated subsequence and of the Nth root of a weighting value, where N is the number of signal elements in each subsequence.

5. The device of claim 3 wherein the amplitude weighting is defined by a function approximated by N line segments, each group of encoded signals comprises N subsequences and said fixed predetermined multiplier value associated with said multiplier means in each subsection is a function of the initial phase of the associated subsequence and of the Nth root of the ratio of the initial and final value of the associated segment of said weighting function.

6. The device of claim 1 further comprising means coupled to each of said subsections for summing the sub-accumulation signals produced by each subsection, to form an output signal substantially equal to amplitude weighted phase decoded value of a group of said applied phase encoded signals.

7. The device of claim 1 wherein each said group of sequentially applied phase encoded signals comprises N2 signals of N phase encoded states;

and said memory device is a shift register having N2 + 1 stages, and N + 1 output circuits coupled to different stages along said shift register with N - 1 stages between adjacent said output circuits.

8. The device of claim 1 wherein each said applied encoded signal has inphase and quadrature signal components;

and said memory device, said plurality of subsections, and said signal modifying means are dual channel devices adapted for processing inphase and quadrature signal components.

9. The device of claim 1 wherein each subsection includes two processing channels with each channel comprising said accumulator means, said means for storing, said multiplier means, and said coupling means;

and said device further comprises control means for selectively controlling the coupling of said coupling means within each of said subsections and the coupling of each channel to said signal modifying means, so that one of said processing channels in each subsection provides the associated sub-accumulation signal during one sequence of alternating sequences of decoding cycles and is cleared and reinitialized during the other sequence, and the other channel is cleared and reinitialized during said one sequence and provides said sub-accumulation signal during said other sequence.

10. The device of claim 3 wherein each subsection includes two processing channels with each channel comprising said accumulator means, said means for storing, said multiplier means, and said coupling means;

and said device further comprises control means for selectively controlling the coupling of said coupling means within each of said subsections, and the coupling of each channel to said signal modifying means, so that one of said processing channels in each subsection provides the associated sub-accumulation signal during one sequence of alternating sequences of decoding cycles and is cleared and reinitialized during the other sequence and the other channel is cleared and reinitialized during said one sequence and provides said sub-accumulation signal during said other sequence.

11. The device of claim 10 wherein said control means includes switching means coupled between the output of said accumulator means in each channel and the associated means for storing, and in the path of said modified subtraction signal applied to said accumulator means in each channel, for alternately enabling one of said processing channels to provide said sub-accumulation signal and for clearing and reintializing the other of said processor channels.

12. The device of claim 9 further comprising means for summing the sub-accumulation signals produced by each said subsection to form an output signal substantially equal to the amplitude weighted phase decoded value of a group of said applied encoded signals;

and summer control means for connecting said one processing channel of each subsection to said means for summing during said one sequence of alternating sequences of decoding cycles and for connecting said other processing channel of each subsection to said means for summing during said other sequence.

13. A device for consecutively decoding groups of sequentially applied phase encoded signals having N2 signals of N phase encoded states in each group, said device comprising:

a memory device having an input circuit for receiving said applied signals and having N + 1 output circuits;

N subsections, each subsection coupled between pairs of output circuits of said memory device and including two processing channels, and each channel comprising accumulator means for forming a sub-accumulation signal which approximates the decoded value of one subsequence of N encoded signals, storage means for storing said sub-accumulation signal and multiplier means coupled between the output of said means for storing and the input of said accumulator means for multiplying said stored sub-accumulation signal by a fixed predetermined value; and

means for selectively controlling the coupling between the output circuits of said memory device associated with each subsection and the channels of each said subsection, and for controlling the coupling between the output of said accumulator means and the input of said storage means in each channel so that each of said channels of each subsection alternately provides said sub-accumulation signal for one sequence of alternating sequences of processing cycles and is alternately cleared and initialized on the next sequence of processing cycles.

14. A device for consecutively decoding groups of sequentially applied phase encoded signals, said device comprising:

a memory unit having an input circuit for receiving said applied signals and having a plurality of output circuits;

a plurality of subsections with each subsection coupled between pairs of output circuits of said memory device and including two processing channels with each channel comprising means for forming a sub-accumulator signal that approximates the phase decoded value of one subsequence of said applied phase encoded signals; and

means for selectively controlling the coupling between the channels of each said subsections and the associated output circuits of said memory device so that one of said processing channels in each subsection provides said sub-accumulation signal during one sequence of alternating sequences of decoding cycles and is cleared and reinitialized during the other sequence of said alternating decoding cycles, and the other channel is cleared and reinitialized during said one sequence and provides said sub-accumulation signal during said other sequence.

15. The device of claim 14 wherein said means for forming said sub-accumulation signal includes accumulator means for forming said sub-accumulation signal in response to input signals applied thereto, storage means for storing said sub-accumulation signal, and multiplier means coupled between the output of said means for storing and one input of said accumulator means for multiplying said stored sub-accumulation signal by a fixed predetermined value;

and said means for selectively controlling includes means for coupling the input of said storage means, to either the output of said associated accumulator means or to one of the associated output circuits of said memory device.

16. The device of claim 15 wherein said groups of applied encoded signals are amplitude weighted and phase decoded therein, and said device further comprises applied signal modifying means coupled between said plurality of output circuits of said memory device and said means for selectively controlling, for providing signals to each subsection so that the stored sub-accumulation signal associated with each subsection is modified as a function of the amplitude weighted difference between the applied encoded signal group associated with said stored sub-accumulation signal and a next signal group, to form a new amplitude weighted phase decoded sub-accumulation signal associated with said next signal group.

17. The device of claim 16 wherein said multiplier means includes means for multiplying said stored subaccumulation signal by a function of the encoded phase of the associated subsequence and of the Nth root of a weighting value, where N is the number of signal elements in each subsequence.

18. The device of claim 16 wherein the amplitude weighting is defined by a function approximated by N line segments, each group of encoded signals comprising N subsequences and said fixed predetermined multiplier value associated with said multiplier means in each subsection is a function of the initial phase of the associated subsequence and of the Nth root of the ratio of the initial and final value of the associated segment of said weighting function.

19. The device of claim 14 wherein each said group of sequentially applied phase encoded signals comprises N2 signals of N phase encoded states;

and said memory device is a shift register having N2 + 1 stages, and N + 1 outputs circuits coupled to different stages along said shift register with N - 1 stages between adjacent said output circuits.

20. The device of claim 14 wherein each said applied encoded signal has inphase and quadrature signal components;

and said memory device, said plurality of subsections, and said means for selectively controlling are dual channel devices adapted for processing inphase and quadrature signal components.

21. A method for consecutively decoding and amplitude weighting groups of sequentially applied signals with each group comprising N2 signals of N phase encoded states and each group differing from the last previously applied group by the addition of a new encoded signal to one end of the group and the deletion of a signal from the other end of the group, said method comprising the steps of:

forming N sub-accumulation signals such that the value of each sub-accumulation signal approximates the amplitude weighted phase decoded value of a subsequence of N encoded signal of a particular group of encoded signals;

storing said N sub-accumulation signals; and

modifying the amplitude and phase of each of said stored sub-accumulation signals as a function of the amplitude weighted and encoded phase difference between the associated subsequence of N encoded signals of said particular group and the next applied group to form a new set of sub-accumulation signals associated with the next group of applied encoded signals.

22. The method of claim 21 further comprising the step of summing said N sub-accumulation signals to form a signal substantially equal to the amplitude weighted phase decoded value of the associated group of encoded signals.

23. The method of claim 21 wherein said storing step comprises alternately storing each sub-accumulation signals in one of two associated storage channels for a first sequence of alternating processing sequences and clearing and reinitializing the other storage channel.

24. A pulse compression system comprising:

means for transmitting phase encoded pulses of energy;

means for receiving reflected energy from said transmitted encoded pulses;

means for sequentially processing said received energy to form a plurality of sub-accumulation signals the sum of which approximates the phase decoded amplitude weighted value of the received energy from a particular range interval;

means for storing said plurality of sub-accumulation signals; and

means for modifying said plurality of stored subaccumulation signals associated with said particular range interval to form a new set of sub-accumulation signals the sum of which approximaTes the phase decoded amplitude weighted value of the energy received from the next range interval.

25. The system of claim 24 wherein:

said transmitting means includes means for encoding N phase states onto N2 signal segments of each transmitted signal;

said storage means includes means for storing N sub-accumulation signals the value of each sub-accumulation signal approximating the amplitude weighted phase decoded value of a subsequence of N received encoded signals; and

said modifying means includes means for modifying each said stored signal as a function of the amplitude weighted and encoded phase difference between said signals associated with a particular range interval and the next range interval.

26. The device of claim 25 wherein said means for storing includes two storage channels associated with each sub-accumulation signal and means for storing each of said sub-accumulation signals in one of said associated storage channels for one sequence of alternating processing sequences, for clearing and reinitializing the other storage channel during said one sequence, and for reversing the storage and the clearing, reinitializing channels during the other sequence of said alternating processing sequences.