COUNTING DIGITAL FILTERS

• US 3,732,409 A
• Filed: 03/20/1972
• Issued: 05/08/1973
• Est. Priority Date: 03/20/1972
• Status: Expired due to Term

• Current Assignee: Shalhav Zohar
• Original Assignee: Shalhav Zohar
• Inventors: Zohar, Shalhav
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Malzahn, David H.
• Application Number:
  US05/236,285
• Time in Patent Office: 414 Days
• Field of Search: 235/164,156,152 328/167 325/42,323
• US Class Current: 708/300
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

Several embodiments of a counting digital filter of the nonrecursive type are disclosed. In each embodiment two registers, at least one of which is a shift register, are included. The shift register receives Jx-bit data input words bit by bit. The kth data word is represented by the integer In the shift register wherein the data words are fed in a monotonic word index sequence, they are separated by Ja-1 spacing zero bits, where Ja represents the number of bits of each of K filter coefficients stored in the other register. The kth filter coefficient is represented by the integer An output sample ym is computed as a function of J components in accordance with the expression J is equal to Ja+Jx-1. The (hr)m'"'"''"'"'s are functions of the bits of the coefficients and data words in accordance with the expression Since the products in the last expression involve binary quantities only, each of them is determined as the output of a two-input AND gate. The double summation is carried out simply by counting all TRUE AND gates.

Claims

1. A digital filter comprising:

first register means for storing K filter coefficients, each of Ja bits, both K and Ja being integers, the kth filter coefficient being represented by the integer wherein ukj 0, 1 and B is one of the group consisting of +2 and -2;

a shift register for storing multibit data words, each of Jx bits, said Jx bits of each word being shifted therein one bit at a time, the kth data word being represented by the integer wherein vkj 0, 1;

means, including counting and gating means, cross-linking said first register means and said shift register for providing each of J components of an output sample as a function of the AND function of selected bits stored in said first register means and said shift register; and

accumulator means for providing an output sample which is a function of said J components, J Ja+Jx-1.

2. The filter as recited in claim 1 wherein each output signal component is definable as uki being the coefficient of Bi in the representation of the filter coefficient ak and vm k, r i is the coefficient of Br 1 in representation of the data word xm k, each product ukivm k, r i being a binary quantity, and said means, including counting and gating means, providing said signal component by counting those of the binary quantities, which are 1'"'"''"'"'s.

3. The filter as recited in claim 2 wherein each data word has associated therewith Ja-1 spacing zero bits, whereby in said shift register data words are spaced by Ja-1 spacing zero bits and each of said (hr)m components is produced by counting those binary quantities which are 1'"'"''"'"'s after a bit of an input data word or a spacing zero bit associated therewith are fed into said shift register.

4. The filter as recited in claim 3 wherein the output sample provided by said accumulator means is definable as

5. The filter as recited in claim 4 wherein said accumulator means provide said output sample ym in accordance with the relationship ym ((hJ 1B+hJ 2) B+ . . . h1) B+h0, wherein h0 through hJ 1 represent the J counts received from said counting means.

6. The filter as recited in claim 4 wherein said gating means include KJa two-input AND gates cross-linking said first register means and said shift register and said counting means are coupled to said KJa gates for providing a count of the AND gates having TRUE outputs, said count representing one component (hr)m, of said output sample, said accumulator means being coupled to said counting means for providing said output sample as a function of the J counts received from said counting means.

7. The filter as recited in claim 6 wherein B -2.

8. The filter as recited in claim 6 wherein said accumulator means provide said output sample ym in accordance with the relationship ym ((hJ 1B+hJ 2) B+ . . . h1)B+h0, wherein h0 through hJ 1 represent the J counts received from said counting means.

9. The filter as recited in claim 8 wherein B -2, and wherein said accumulator means includes a sign bit which is reversed each time a count is received by said accumulator means from said counting means.

10. The filter as recited in claim 6 wherein said counting means comprises a plurality Of counters including a group of counters each serially counting a different group of TRUE AND gates out of said KJa gates, with all of said counters in said group counting corresponding gates in parallel, with the rest of said counters combining the contents in said group of counters into a single count representing a component of said output sample.

11. The filter as recited in claim 10 wherein said accumulator means provide said output sample ym in accordance with relationship ym ((hJ 1B+ hJ 2) B+ . . . h1)B+h0 wherein h0 through hJ 1 represent the J counts received from said counting means.

12. The filter as recited in claim 11 wherein B -2, and wherein said accumulator means includes a sign bit which is reversed each time a count is received by said accumulator means from said counting means.

13. The filter as recited in claim 11 wherein said KJa gates are divided into P substantially equal groups, the number of gates in each group being equal to q, wherein q 2d-1 and wherein each counter in said group of counters is a d-bit binary counter, both q and d being integers.

14. The filter as recited in claim 13 wherein B -2, and wherein said accumulator means includes a sign it which is reversed each time a count is received by said accumulator means from said counting means.

15. The filter as recited in claim 4 wherein said counting and gating means include KJa two-input AND gates cross-linking said first register means and said shift register, and signal producing means for providing each component as an analog signal having a value hr Br, and said accumulator means comprises means for accumulating said J components from r 0 to r J-1 to provide said output sample.

16. The filter as recited in claim 15 wherein said signal producing means include KJa equal resistors connected in parallel between first and second terminals, each resistor being connected in series with a separate switch means between said terminal, each switch means being closed to provide a current path thereacross when the output of an AND gate associated therewith is TRUE, means coupled to said first terminal for providing a potential proportional to Br as the component (hr)m is produced, whereby the total current amplitude passing through said KJa resistors is proportional to hrBr, and said accumulator means is a current integrator connected to said second terminal for providing said output sample ym after integrating the currents representing said J components.

17. The filter as recited in claim 16 wherein B -2.

18. The filter as recited in claim 4 wherein said gating means include KJa two-input AND gates cross-linking said first register means and said shift register and said counting means comprises a single counter coupled to said KJa gates for serially counting said gates to provide a count of the AND gates having TRUE outputs, said count representing one component of said output sample, said accumulator means being coupled to said counting means for providing said output sample as a function of the J counts received from said counting means.

19. The filter as recited in claim 18 wherein B -2.

20. The filter as recited in claim 18 wherein said accumulator means provide said output sample ym in accordance with the relationship ym ((hJ 1B+hJ 2)B+ . . . h1)B+h0, wherein h0 through hJ 1 represent the J counts received from said counting means.

21. The filter as recited in claim 20 wherein B -2, and wherein said accumulator means includes A sign bit which is reversed each time a count is received by said accumulator means from said counting means.

22. The filter as recited in claim 4 wherein said first register means comprises a first circulating line with Jx-1 spacing zero bits between adjacent filter coefficients, said gating means comprises a single two-input AND gate coupled to one cell of each of said first circulating line and said shift register, and means coupled to the input and output cells of said shift register for controlling the supply to said input cell, of the content of the output cell or an input bit.

23. The filter as recited in claim 22 wherein the counting means and the accumulator means comprise a multistage counter coupled to said single gate to receive a count of one each time the gate output is TRUE and control means coupled to said counter for controlling the stage of the counter which receives said count as a function of the component being produced.

24. The filter as recited in claim 23 wherein B -2, said counter is an UP-DOWN counter and said control means controls said counter to count down when r is odd and up when r is other than odd.