FRAME SYNCHRONIZATION SYSTEM FOR A DIGITAL COMMUNICATION SYSTEM

• US 3,735,045 A
• Filed: 08/24/1970
• Issued: 05/22/1973
• Est. Priority Date: 08/24/1970
• Status: Expired due to Term

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: James M. Clark
• Inventors: Clark, James M.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Martin, John C.
• Application Number:
  US05/066,258
• Time in Patent Office: 1,002 Days
• Field of Search: 178/69.5R,69.5F,7.35,7.55 179/15BS 328/127,151,155 307/228,233,269 235/183 325/38B
• US Class Current: 375/373
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00

Abstract

A framing control circuit for a frame synchronization system employing one integrator for both the sense and search modes rather than a separate integrator for each of the sense and search modes. A voltage controlled amplitude control circuit is disposed at the input to the integrator. The control signal for the control circuit is produced by a bistable device coupled to the output of the integrator. A low binary control signal, indicating a sense mode, provides a relatively low amplitude input signal to the integrator and, hence, an effective long time constant for the integrator. A high binary control signal, indicating a search mode, provides a relatively large amplitude input signal to the integrator and, hence, an effective short time constant for the integrator.

Claims

1. A frame synchronization system comprising:

a source of binary information signal having a given bit rate and containing a synchronization component;

first means to produce a plurality of timing signals;

second means coupled to said source and said first means to examine successive bits of said information signal to recognize said synchronization component and produce a resultant output signal at each examination indicating either an insynchronization condition or an out-of-synchronization condition;

third means to integrate said resultant output signal;

fourth means coupled to the output of said third means responsive to the integrated output signal thereof to produce a first control signal indicating either an in-synchronization condition or an out-of synchronization condition;

fifth means coupled between said second and third means and to said fourth means responsive to said first control signal to adjust the amplitude of said resultant output signal applied to said third means to enable said third means to perform a slow integration of said resultant output signal for an insynchronization condition of said first control signal and a fast integration of said resultant output signal for an out-ofsynchronization condition of said first control signal; and

sixth means coupled to said first means, said second means, said third means and said fourth means to provide a second control signal for timing adjustment of said timing signals when said resultant output signal and said first control signal indicate an out-of-synchronization condition and the amplitude of the result of said fast integration of said third means has exceeded a given value.

2. A system according to claim 1, wherein said first means further produces a local binary synchronization reference signal;

and said second means includes digital comparison means coupled to said source and said first means to compare the binary condition of successive bits of said information signal and the binary condition of said reference signal and produce said resultant output signal.

3. A system according to claim 1, wherein said third means includes an operational amplifier having an inverting input, a non-inverting input and an output, a resistor coupled between said fifth means and said inverting input, a capacitor coupled between said output and said inverting input, a clamp circuit coupled between said output and said inverting input to prevent the output signal of said amplifier at any time from going below a given fixed voltage, a bias source coupled to said non-inverting input, and means coupled between said fourth means and said non-inverting input responsive to said first control signal to adjust the amplitude of the bias voltage on said non-inverting input in step with the adjustment of the amplitude of said resultant output signal.

4. A system according to claim 1, wherein said fourth means includes a bistable device.

5. A system according to claim 4, wherein said bistable device includes an operational amplifier having an inverting input, a non-inverting input and an output, a bias source coupled to said inverting input, means coupling said non-inverting input to the output of said third means, a feedback means coupled between said output and said non-inverting input, and means coupling said first control signal from said output.

6. A system according to claim 1, wherein said third means includes a first operational amplifier having an inverting input, a non-inverting input and an output, a resistor coupled between said fifth means and said inverting input of said first amplifier;

a capacitor coupled between said output and inverting input of said first amplifier, a clamp circuit coupled between said output and inverting input of said first amplifier to prevent the output signal of said first amplifier at any time from going below a given fixed voltage, a first bias source coupled to said inverting input of said first amplifier, and seventh means coupled between said fourth means and said non-inverting input of said first amplifier responsive to said first control signal to adjust the amplitude of the bias voltage on said non-inverting input of said first amplifier in step with the adjustment of the amplitude of said resultant output signal; and

said fourth means includes a bistable device including a second operational amplifier having an inverting input, a non-inverting input and an output, a second bias source coupled to said inverting input of said second amplifier, eighth means coupling said non-inverting input of said second amplifier to said output of said first amplifier, a feedback means coupled between said output and said non-inverting input of said second amplifier, and ninth means coupling said first control signal from said output of said second amplifier to said fifth means and said seventh means.

7. An integration system having an adjustable time constant comprising:

a source of input signal to be integrated;

first means to integrate said input signal;

second means coupled to the output of said first means responsive to the integrated output signal to produce a control voltage; and

a voltage controlled amplitude control means coupled between said source and said first means and to said second means responsive to said control voltage to adjust the amplitude of said input signal applied to said first means from said source and thereby adjust the effective time constant of said first means;

said input signal being a binary signal;

said control voltage being a binary signal;

said voltage controlled amplitude control means responding to one binary condition of said control voltage to provide said first means with a first effective time constant and the other binary condition of said control voltage to provide said first means with a second effective time constant different than said first effective time constant; and

said second means including a bistable device;

said bistable device including an operational amplifier having an inverting input, a non-inverting input and an output, a bias source coupled to said inverting input, means coupling said non-inverting input to the output of said first means, a feedback means coupled between said output and said non-inverting input, and means coupling said control voltage from said output.

8. An integration system having an adjustable tiMe constant comprising:

a source of input signal to be integrated;

first means to integrate said input signal;

second means coupled to the output of said first means responsive to the integrated output signal to produce a control voltage; and

a voltage controlled amplitude control means coupled between said source and said first means and to said second means responsive to said control voltage to adjust the amplitude of said input signal applied to said first means from said source and thereby adjust the effective time constant of said first means;

said first means including an operational amplifier having an inverting input, a non-inverting input and an output, a resistor coupled between said amplitude control means and said inverting input, a capacitor coupled between said output and said inverting input, a clamp circuit coupled between said output and said inverting input to prevent the output signal of said amplifier at any time from going below a given fixed voltage, a bias source coupled to said non-inverting input, and means coupled between said second means and said non-inverting input responsive to said control signal to adjust the amplitude of the bias voltage of said non-inverting input in step with the adjustment of the amplitude of said input signal.

9. A system according to claim 8, wherein said input signal is a binary signal, said control voltage is a binary signal, and said voltage controlled amplitude control means responds to one binary condition of said control voltage to provide said first means with a first effective time constant and the other binary condition of said control voltage to provide said first means with a second effective time constant different than said first effective time constant.

10. A system according to claim 9, wherein said second means includes a bistable device.

11. A system according to claim 10, wherein said bistable device includes an operational amplifier having an inverting input, a non-inverting input and an output, a bias source coupled to said inverting input, means coupling said non-inverting input to the output of said first means, a feedback means coupled between said output and said non-inverting input, and means coupling said control voltage from said output.

12. An integration system having an adjustable time constant comprising:

a source of input signal to be integrated;

first means to integrate said input signal;

second means coupled to the output of said first means responsive to the integrated output signal to produce a control voltage; and

a voltage controlled amplitude control means coupled between said source and said first means and to said second means responsive to said control voltage to adjust the amplitude of said input signal applied to said first means from said source and thereby adjust the effective time constant of said first means;

said first means including a first operational amplifier having an inverting input, a non-inverting input and an output, a resistor coupled between said amplitude control means and said inverting input of said first amplifier, a capacitor coupled between said output and inverting input of said first amplifier, a clamp circuit coupled between said output and inverting input of said first amplifier to prevent the output signal of said first amplifier at any time from going below a given fixed voltage, a first bias source coupled to said non-inverting input, and third means coupled between said second means and said non-inverting input of said first amplifier responsive to said control voltage to adjust the amplitude of the bias voltage on said non-inverting input of said first amplifier in step with the adjustment of the amplitude of said input signal; and

said second means including a second operational amplifier having an inverting input, a non-inverting input and an output, a second biaS source coupled to said inverting input of said second amplifier, fourth means coupling said non-inverting input of said second amplifier to said output of said first amplifier, a feedback means coupled between said output of said second amplifier and said non-inverting input of said second amplifier, and fifth means coupling said control signal from said output of said second amplifier to said amplitude control means and said third means.