SHIFT REGISTER INTERCONNECTION SYSTEM

• US 3,735,362 A
• Filed: 09/22/1971
• Issued: 05/22/1973
• Est. Priority Date: 09/22/1971
• Status: Expired due to Term

• Current Assignee: Leo M. Audretsch Jr, Michael J. Pisterzi, Ron Ashany
• Original Assignee: Leo M. Audretsch Jr, Michael J. Pisterzi, Ron Ashany
• Inventors: Ashany, Ron, Audretsch, Leo M. Jr., Pisterzi, Michael J.
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Thomas, James D.
• Application Number:
  US05/182,775
• Time in Patent Office: 608 Days
• Field of Search: 340/172.5
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4213 with asynchronous protocol
• CPC Class Codes: H04L 12/4637 Interconnected ring systems

Abstract

Units of a data processing system communicate on a ring connection of shift register stages. The number of stages in a shift register is made small to avoid the delays that accompany the long data paths of a large ring system. Interconnecting stages are provided to direct a message on a first ring to a second ring according to an address contained in the message. Several useful configurations are disclosed. With this arrangement, a system of small rings can be expanded without correspondingly lengthening the average time for transmitting a message in the system.

Claims

1. A ring shift register system for a data processing system comprising:

a plurality of ring connections of shift register stages interconnected to shift a message in a predetermined direction from one stage to another, said message having an address portion defining one of said plurality of rings and a destination unit in the addressed ring, each said stage having register means for holding a message applied to the stage, means for reading an address portion of a message, and means responsive to an address to direct a message to the next stage or to an addressed load associated with the stage, and an interconnection stage connected between a first ring and a second ring and having means to transfer messages from the preceding stage to the next stage of the same ring or to the next stage of an addressed one of the other ring according to the address portion of the message.

2. The system of claim 1 Wherein said interconnection stage comprises buffer means, register means for each ring for holding a message transferred to the interconnection stage from the preceding stage of a ring, logic means for comparing the address portion of a message with a predetermined address distinguishing one ring from another, and means responsive to said address comparing means to enter messages into said buffer means.

3. The system of claim 2 wherein said logic means comprises means responsive to a vacancy in said register means for entering a message from said buffer into the addressed ring.

4. The system of claim 3 comprising first, second and third rings, an interconnection stage connecting said first ring to a first point on said third ring, a second interconnection stage connecting said second ring to a second point on said third ring, and means in each said interconnection stage to transfer messages from one ring to another or to the next stage of the same ring according to the address portion of the message.

5. The system of claim 4 comprising a plurality of interconnection stages connecting said first and second rings, the connection of said interconnection stages of said rings defining ring segments having intervening register stages and means in each of said interconnection stages for routing messages from one of said segments to another according to said address.

6. The system of claim 3 comprising a third and a fourth ring, a second interconnection stage connecting said first and third rings, a third interconnection stage connecting said third and fourth rings, and a fourth interconnection stage connecting said fourth and second rings.

7. The system of claim 6 further comprising a fifth interconnection stage connecting said first and fourth rings and a sixth interconnection stage connecting said second and third rings.

8. The system of claim 5 wherein said logic means includes means for comparing the destination address of a message with a plurality of destination ring segment addresses for accepting messages according to a predetermined routing.

9. The system of claim 8 wherein said comparing means comprises means holding a plurality of destination segment addresses and means comparing said segment addresses with a message address for accepting a message according to a predetermined routing.

10. A ring shift register system for a data processing system comprising:

a first, second and third ring of shift register stages, each of said stages having register means for holding a message applied to the stage, means for reading an address portion of a message, gating circuits responsive to said address to direct said message to a next stage of the ring or to remove said message from said ring, and means responsive to a vacancy in said stage for entering messages in the ring, and means interconnecting two of said stages in each ring and one of said stages in each other ring to form interconnection stages in which messages are transferred from ring to ring or to the next stage in the same ring according to the address.