LOW PHASE NOISE DIGITAL FREQUENCY DIVIDER

• US 3,737,676 A
• Filed: 11/18/1971
• Issued: 06/05/1973
• Est. Priority Date: 11/18/1971
• Status: Expired due to Term

• Current Assignee: Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, George F. Lutes Jr, N/a,
• Original Assignee: Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, George F. Lutes Jr, N/a,
• Inventors: Fletcher, James C. Administrator of the National Aeronautics and Space, N/a,, Lutes, George F. Jr.
• Primary Examiner(s): Huckert, John W.
• Assistant Examiner(s): Hart, R. E.
• Application Number:
  US05/199,957
• Time in Patent Office: 565 Days
• Field of Search: 307/167,220,225,226,232,233,240 328/25,30,37-39,42,15
• US Class Current: 327/117
• CPC Class Codes: H03B 19/00 Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source transference of modulation from one carrier to another H03D7/00
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A low phase noise frequency divider is disclosed comprising a gating arrangement which supplies selected portions of an input reference signal to be divided to a tuned circuit without any phase noise due to the gating action. The arrangement which in one embodiment consists of a FET is connected to the tuned circuit input to short out the input except when the input reference signal amplitude crosses ground level in a positive direction and a gate enabling signal is present at the gate electrode of the FET. The gate-enabling signal alone does not decouple the tuned circuit input from ground, therefore phase noise, due to the leading and trailing edges of each gateenabling signal, is substantially eliminated.

Claims

1. In a frequency divider the arrangement comprising:

a source of an input signal which varies sinusoidally about a reference level at a frequency f, each cycle of said signal having a positive half cycle and a negative half cycle with respect to said reference level;

a tuned amplifier tuned to a frequency f/n where n is an integer;

control means for generating a succession of control signals at a frequency f/n, each control signal having a duration between its leading and trailing ends which is greater than 1/2 cycle and less than 3/2 cycles of the input signal, said control means including phase shifting means for controlling the phase between said input signal and said control signal so that a selected portion of every nth cycle of said input signal occurs during the duration of a different control signal other than during the leading and trailing ends thereof; and

gating means coupled to the input of said tuned amplifier and responsive to said input signal and each control signal for inhibiting the level at the input of said tuned amplifier to vary from a preselected reference level in the absence of a control signal and during the leading and trailing ends of each control signal and for controlling the level at the input of said tuned amplifier to vary in a manner corresponding to the change of level of the input signal during a selected portion of every nth cycle of said input signal which is in time coincidence with a control signal other than during the leading and trailing ends thereof, said selected portion being not more than one half cycle.

2. In a frequency divider the arrangement comprising:

isolation means for receiving an input signal which varies sinusoidally about a reference level, definable as ground, at an input frequency definable as f, to be divided by a factor n, n being an integer and for providing a corresponding output signal at an output terminal of said isolation means;

division control means for providing a succession of control signals at one nth the frequency of said input signal, each control signal having a duration which is greater than 1/2 cycle of said input signal and less than 3/2 cycles of said inpUt signal;

a tuned amplifier tuned to one nth the frequency of said input signal;

gating means coupled between said output terminal and the input of said tuned amplifier and responsive to said control signals and the output signal at said output terminal for grounding the input of said tuned amplifier except during a portion of the duration of each control signal which is in time coincidence with a selected portion of a cycle of said output signal, said selected portion being not more than half a cycle, whereby the input of said tuned amplifier is ungrounded only during the selected portion of every nth cycle of said output signal; and

output means responsive to the output of said tuned amplifier for providing a sinusoidal signal at one nth the frequency of the input signal.

3. The arrangement as described in claim 2 wherein said gating means comprises a field effect transistor with drain source and gate electrodes, means for grounding said source electrode, means for applying said control signal to said gate electrode and means for connecting said drain electrode to the input of said tuned amplifier and said output terminal, each control signal having a negative polarity with respect to ground, whereby said field effect transistor provides a low resistive path for the input of said tuned amplifier to ground during the duration of each control signal except when the level at said drain electrode is positive with respect to the level at said gate electrode, whereby the input of said tuned amplifier is ungrounded only during the positive half cycle of each nth cycle of said output signal.

4. The arrangement as described in claim 2 wherein said division control means include phase shifting means for controlling the relative phase between said control signals and said output signal so that each selected portion of a cycle of said output signal occurs during the duration of another control signal other than at the leading or trailing ends thereof, so as to inhibit said tuned amplifier from sensing said leading or trailing ends.

5. The arrangement as described in claim 4 wherein said gating means comprises a field effect transistor with drain source and gate electrodes, means for grounding said source electrode, means for applying said control signals to said gate electrode and means for connecting said drain electrode to the input of said tuned amplifier and said output terminal, each control signal having a negative polarity with respect to ground, whereby said field effect transistor provides a low resistive path for the input of said tuned amplifier to ground during the duration of each control signal except when the level at said drain electrode is positive with respect to the level at said gate electrode, whereby the input of said tuned amplifier is ungrounded only during the positive half cycle of each nth cycle of said output signal.