PARASITIC SUPPRESSING CIRCUIT

• US 3,737,757 A
• Filed: 05/15/1972
• Issued: 06/05/1973
• Est. Priority Date: 05/15/1972
• Status: Expired due to Term

• Current Assignee: Frank L. Raposa, John T. Fowler
• Original Assignee: Frank L. Raposa, John T. Fowler
• Inventors: Fowler, John T., Raposa, Frank L.
• Primary Examiner(s): Shoop, Jr., William M.
• Application Number:
  US05/253,405
• Time in Patent Office: 386 Days
• Field of Search: 317/DIG.6 321/11,12,13,45C
• US Class Current: 363/135
• CPC Class Codes: H02H 9/007 avoiding or damping oscillations, e.g. fenoresonance or travelling waves
• CPC Class Codes: H02M 7/523 with LC-resonance circuit in the main circuit

Abstract

A circuit for suppressing parasitic oscillations across an inductor operating in a resonant mode is described. The circuit includes a switch means and resistive means connected serially across the inductor. A unidirectional resistive-capacitive network is also connected across the inductor and to the switch means to automatically render the switch means conducting when inductive current through the inductor ceases to flow.

Claims

1. A parasitic oscillation suppressor for use with a power inductor of a resonant type inverter, said suppressor comprising:

switch means having power electrodes and a control electrode;

first voltage dropping means connected seriallY with said power electrodes of said switch across said power inductor;

second and third voltage dropping means connected serially between one end of said power inductor and the other end of same;

first unidirectional conducting means and first energy storage means connected serially in the order mentioned between said one end of said power inductor and a point intermediate said second and third voltage dropping means; and

means connecting a point intermediate said first unidirectional conducting means and said first energy storage means to said control electrode of said switch means.

2. The circuit of claim 1 wherein said first, second and third voltage dropping means are resistors.

3. The circuit of claim 1 and including a second unidirectional conducting means connected between said third voltage dropping means and said other end of said power inductor and poled to pass current in the same direction as said first unidirectional conducting means.

4. The circuit of claim 3 wherein said switch means is a solid-state controlled rectifier having anode, cathode and gate electrodes.

5. The circuit of claim 4 and including second energy storage means connected between said anode and said cathode of said controlled rectifier, and third unidirectional conducting means connected in series with said first voltage dropping means between said second energy storage means and said other end of said inductor, said third unidirectional conducting means being poled to pass current in the same direction as said SCR.

6. The circuit of claim 5 and including fourth voltage dropping means connected between said gate electrode and said one end of said power inductor.

7. The circuit of claim 5 wherein said first and second energy storage means are capacitors.

8. The circuit of claim 5 wherein said first and second unidirectional conducting means are solid-state diodes.

9. A parasitic oscillation suppressor for use with a power inductor of a resonant type inverter, said suppressor comprising switch means having power electrodes and a control electrode;

first voltage dropping means connected serially with said power electrodes of said switch across said power inductor;

a first capacitor connected to said control electrode of said switch means;

means for charging said capacitor during the inductive half cycle of the power inductor; and

means for limiting the discharge rate of said capacitor whereby the discharge time of said capacitor is of adequate duration to render said switch means conducting.