DIGITAL VOLTMETER

• US 3,737,891 A
• Filed: 05/07/1971
• Issued: 06/05/1973
• Est. Priority Date: 05/11/1970
• Status: Expired due to Term

• Current Assignee: Eric Metcalf
• Original Assignee: Eric Metcalf
• Inventors: Metcalf, Eric
• Primary Examiner(s): Robinson, Thomas A.
• Assistant Examiner(s): Glassman, Jeremiah
• Application Number:
  US05/141,327
• Time in Patent Office: 760 Days
• Field of Search: 340/347NT,347CC,347AD 324/130,99,115 235/154
• US Class Current: 341/118
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/02 Reversible analogue/digital converters

Abstract

An input voltage is converted to a digital output by applying the voltage to a voltage to frequency converter whose output is counted for a measured interval. To obtain high digital resolution with a short measurement interval, the v to f frequency at full scale input is very high. The voltmeter is linearized by completing a loop from the v to f converter, through a frequency divider and a standard charge generator supplying a fixed pulse of charge for each pulse from the divider, to a smoothing circuit which provides a voltage opposing the input voltage. The frequency divider is included because of the said high frequency, but then the slow speed of the pulses from the divider at small inputs causes the fixed pulses of charge to be inadequately smoothed. Therefore a digital to analogue converter is driven off the frequency divider binary stages to provide a periodic staircase ramp function which is a.c. coupled into the smoothing circuit to cancel out the a.c. component of the inadequately smoothed pulses. Auto-calibration is provided at both plus and minus full scale input, enabling both zero offset and slope of the voltmeter calibration line to be corrected.

Claims

1. An analogue to digital converter comprising a voltage to frequency converter responsive to the voltage difference between the input voltage and a feedback voltage to provide pulses at a rate proportional to the input voltage;

and a feedback circuit responsive to said pulses to provide the feedback voltage, said feedback circuit comprising counter means for dividing said pulses by a number N to provide further pulses, a smoothing filter, charge generating means responsive to each of said further pulses for feeding a fixed pulse charge into said smoothing filter whose output provides the feedback voltage, a digital to analogue converter responsive to said counter means to provide an analog signal, and a.c. coupling means for coupling said analog signal into said smoothing filter said analog signal having a cyclic staircase waveform which at least partially cancels the a.c. component of the smoothed pulses of charge.

2. An analogue to digital converter according to claim 1, wherein said counter means is a binary counter and said charge generating means responds to a most significant bit from said counter means going to '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' and a signal from said charge generating means sets a most significant element of said counter means to '"'"''"'"''"'"''"'"'0'"'"''"'"''"'"''"'"' synchronously with the end of the said fixed pulse charge.

3. An analogue to digital converter according to claim 2, wherein said counter means comprises a most significant portion with a plurality of stages each of which, when set to '"'"''"'"''"'"''"'"'1,'"'"''"'"''"'"''"'"' contributes an input of one most significant bit to the digital to analogue converter, this most significant portion having a datum state in which one stage is set to '"'"''"'"''"'"''"'"' 1,'"'"''"'"''"'"''"'"' being responsive to the preceding portion of the counter to count up to one each time the said preceding portion overflows and being responsive to the charge generating means to count down one synchronously with the end of the said fixed pulse of charge.

4. An analogue to digital converter according to claim 3, comprising means responsive to the presence of three '"'"''"'"''"'"''"'"'1'"'"''"'"'s'"'"''"'"''"'"''"'"' in the said most significant portion to signal an overload condition.

5. An analogue to digital converter according to claim 4, wherein the means which signal an overload condition inhibit the voltage to frequency converter so long as the overload condition is signalled.

6. An analogue to digital converter according to claim 1, wherein the said a.c. coupling means comprises a capacitor in parallel circuit arrangement with said smoothing filter.

7. An analogue to digital converter according to claim 1 wherein said feedback circuit comprises a differeNtial amplifier with an output terminal and two input terminals and a source of a reference offset voltage, the feedback voltage being applied to one input terminal of said differential amplifier and said reference offset voltage is applied to said other input terminal of said differential amplifier whose output provides the voltage which is differenced with the input voltage.

8. An analogue to digital converter according to claim 7, comprising a smoothing capacitor in parallel circuit arrangement with said differential amplifier.

9. An analogue to digital converter according to claim 7, further comprising a range switching attenuator connected to attenuate the feedback voltage output of said differential amplifier.

10. An analogue to digital converter according to claim 1, further comprising automatic calibration circuit means for effecting calibration with a selected one of two different reference inputs including means for deriving two corresponding calibration voltages, and means responsive to these two calibration voltages for deriving both an offset correction voltage for correcting zero offset and a slope correction voltage which adjusts the slope of the frequency to voltage converter.

11. An analogue to digital converter according to claim 10, wherein the offset correction voltage is combined with the feedback voltage.

12. An analogue to digital converter according to claim 10, comprising a chopper arranged to operate synchronously with said charge generating means to chop the slope correction voltage, the output of said chopper being fed into said smoothing filter.

13. An analogue to digital converter according to claim 10, wherein the two reference inputs are opposite but equal voltages, the offset correction voltage is proportional to one of said two calibration voltages, and the slope correction voltage is the mean of said two calibration voltages.

14. An analogue to digital converter according to claim 10, and further comprising a measurement counter for counting the pulses from the voltage to frequency converter, wherein the calibration circuit is adapted, following measurement of each reference input, to apply correction pulses to said measurement counter, thereby to adjust said measurement counter to a reference count corresponding to the reference input, the calibration circuit comprising for each reference input a corresponding integrating circuit arranged to integrate the correction pulses to derive the corresponding calibration voltage.

15. An analogue to digital converter of the type comprising a voltage to frequency converter responsive to the input voltage, further comprising a counter responsive to the output of the voltage to frequency converter to count in one sense, and means for causing the counter to count in the other sense at intervals, which intervals are short compared with the measurement interval, whereby so long as no overload input exists the counts in the other sense balance those in the one sense, whereas an overload input causes the counter to reach a particular state signalling the overload.

16. An analogue to digital converter according to claim 15, comprising a charge generating circuit which generates a fixed pulse of charge each time the counter counts in one sense, means for smoothing the fixed pulses of charge to generate a feedback voltage opposing the input voltage, and wherein the counter is caused to count in the other sense at the end of each said fixed pulse of charge.

17. An analogue to digital converter according to claim 15, comprising means for inhibiting the voltage to frequency converter when an overload is signalled.

18. An analogue to digital converter according to claim 15, wherein the counter comprises a plurality of bistable flip-flops, first gates and second gates, the flip-flops being connected in a ring firstly through the first gates which, when enabled, cause a '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' in any flip-flop to propagate also into the next flip-flop, and secondly through the second gates which, when enabled, cause a '"'"''"'"''"'"''"'"'0'"'"''"'"''"'"''"'"' in any flip-flop to propagate also into the next flip-flop, the counter being caused to count in the one sense and the other sense by enabling the first and second gates respectively.

19. An analogue to digital converter comprising a voltage to frequency converter responsive to the difference between the input voltage and a feedback voltage to provide pulses at a rate proportional to the input voltage, a frequency to voltage converter responsive to the said pulses to provide the feedback voltage, and an automatic calibration circuit arranged to effect calibration with two different reference inputs and to derive two corresponding calibration voltages, and means responsive to these two voltages to derive both an offset correction voltage for correcting zero offset and a slope correction voltage which adjusts the slope of the frequency to voltage converter.

20. An analogue to digital converter according to claim 19, wherein the offset correction voltage is combined with the feedback voltage.

21. An analogue to digital converter according to claim 19, comprising a chopper arranged to chop the slope correction voltage synchronously with the said pulses, the output of the chopper being fed into the frequency to voltage converter in combination with the said pulses.

22. An analogue to digital converter according to claim 19, wherein the two reference inputs are opposite but equal voltages, the offset correction voltage is one of the two calibration voltages, and the slope correction voltage is the mean of the two calibration voltages.

23. An analogue to digital converter according to claim 19, comprising a measurement counter which counts the pulses from the voltage to frequency converter, wherein the calibration circuit is adapted, following measurement of each reference input, to apply correction pulses to the measurement counter, thereby to adjust the measurement counter to a reference count corresponding to the reference input, the calibration circuit comprising for each reference input a corresponding integrating circuit arranged to integrate the correction pulses to derive the corresponding calibration voltage.