DRIVING CIRCUITS FOR LIGHT EMITTING DIODES

• US 3,740,570 A
• Filed: 09/27/1971
• Issued: 06/19/1973
• Est. Priority Date: 09/27/1971
• Status: Expired due to Term

• Current Assignee: George R. Kaelin, James A. Pellegrino
• Original Assignee: George R. Kaelin, James A. Pellegrino
• Inventors: Kaelin, George R., Pellegrino, James A.
• Primary Examiner(s): Schaefer, Robert K.
• Assistant Examiner(s): Smith, William J.
• Application Number:
  US05/184,076
• Time in Patent Office: 631 Days
• Field of Search: 307/40 315/169TV 340/324R,166EL,334,343 178/5.4EL,7.3D 317/235
• US Class Current: 307/40
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

LEDs are arranged in a matrix and driven by a pair of registers. A column register sequentially enables the columns of LEDs and a row register selectively operates the LEDs of each column in accordance with a predetermined binary code. A color control and a brightness control circuit may be included in connection with the row register to selectively control driving currents to the LEDs to control color hue, and to selectively control the duration of '"'"''"'"''"'"''"'"'on'"'"''"'"''"'"''"'"' time to control apparent brightness.

Claims

1. Apparatus for driving selected ones of m times n light emitting diodes where m and n are whole numbers, comprising:

first register means having at least m outputs and second register means having n outputs, each output of said first register means being connected to one side of one diode in each of n mutually exclusive groups of diodes and each output of said second register means being connected to the other side of one diode in each of m mutually exclusive groups of diodes, each diode being in one of said groups of m diodes and in one of said groups of n diodes;

storage means connected to said first register means for storing at least m times n bits representative of information to be displayed, said storage means having a feedback path for recycling m times n bits, and clock means connected to said storage means and to said first register means for initiating said storage means to transfer a binary code containing at least m bits to said first register means for conditioning selected groups of said m groups of diodes for conduction, said clock means further conditioning said second register means for conditioning a group of said n groups of diodes for conduction, diodes existing in both the selected groups of m diodes and the selected group of n diodes being operated for a predetermined period of time, said clock means sequentially conditioning said storage means to transfer successive said binary codes to said first register means and shifting said second register means to operate diodes existing in both the selected groups of m groups of Diodes and the selected group of n groups of diodes until selected diodes in each group of said n groups of diodes are operated, said storage recycling m times n bits to repeat the pattern of operating said diodes.

2. Apparatus according to claim 1 wherein said first register means includes m current source means connected to respective outputs of said first register means, each of said current source means being conditioned by said first register means to provide a predetermined current to the diodes of a respective group of n diodes.

3. Apparatus according to claim 2 wherein said second register means includes n switch means connected to respective outputs of said second register means, each of said switch means providing a current path between the diodes of a respective group of m diodes and said current source means.

4. Apparatus according to claim 2 wherein said diodes are characterized by emitting predominantly different color hues when driven by respectively different currents, and wherein each of said current source means includes a plurality of current sources each adapted to supply a current of mutually different predetermined magnitudes, and means responsive to the binary code in said first register means for selectively connecting on of said current sources to the respective group of n diodes.

5. Apparatus according to claim 4 wherein the binary code transferred to said first register means contains at least 2 m bits, and each of said current source means includes decoder means for decoding 2 bits of said binary code in said first register means to selectively operate said current sources.

6. Apparatus according to claim 4 further including brightness control means for operating said current sources for a predetermined period of time.

7. Apparatus according to claim 6 wherein said brightness control means comprises means responsive to a predetermined code in said first register means for controlling the duration of time that current from the selected current source is applied to the respective group of n diodes.

8. Apparatus according to claim 6 wherein said binary code transferred to said first register means contains at least five m bits, said current source means including first decoder means for decoding two of said bits to selectively operate said current sources and said brightness control means including second decoder means for decoding three of said bits for selectively controlling the duration of operation of said selected diodes.

9. A driving circuit for energizing light emitting diodes of the class which emit predominantly different color hues when driven by respectively different currents, said circuit including current source means adapted to selectively provide one of a plurality of different predetermined current magnitudes;

output means adapted to be connected to said diodes; and

decoder means responsive to a binary input code for selectively connecting said current source means to said output means.

10. Apparatus according to claim 9 wherein said current source means comprises at least three current sources each capable of providing a different current magnitude and said decoder means is adapted to receive a two-bit binary signal to decode said signal to selectively connect one of said current sources to said output means.

11. Apparatus according to claim 9 further including control means for operating said decoder means for a predetermined period of time.

12. Apparatus according to claim 11 wherein said control means comprises second decoder means responsive to a binary input code for controlling the duration of time that current from said current source means is applied to said output.

13. Apparatus according to claim 11 wherein said binary input code includes at least five bits, said first-named decoder means being responsive to at least two of said bits to selectively connect said current magnitudes to said output means, and said control means inCludes second decoder means responsive to at least three of said bits for selectively controlling the duration of operation of said first-named decoder means.

14. Apparatus according to claim 13 wherein said current source means comprises at least three current sources each capable of providing a mutually exclusive current magnitude and said decoder means is adapted to receive a two-bit binary signal to decode said signal to selectively connect one of said current sources to said output means.

15. Apparatus according to claim 1 wherein said first register means produces x m output bits, m number of circuit means each responsive to mutually exclusive x number of bits for producing driving currents each having a current amplitude dependent upon the bit pattern of said respective x number of bits, and means connecting each of said circuit means to respective ones of said groups of n diodes.

16. Apparatus according to claim 15 wherein each of said circuit means is responsive to a respective x number of bits to produce a driving pulse having a current amplitude and a time duration dependent upon the bit pattern of said respective x number of bits.

17. Apparatus according to claim 1 wherein said second register means conditions said groups of m diodes in sequence, whereby diodes in a single group of m diodes as selected by said second register means are operated by said first register means.